access icon openaccess Reliability and performance of optimised Schmitt trigger gates

This study compares the performance and reliability of classical complementary metal-oxide-semiconductor (CMOS) gates with Schmitt trigger (ST) ones. The ST hysteresis, caused by the added positive feedback transistors, improves the design static noise margin (SNM) and offers noise immune operation. Hence, ST-based circuits are expected to operate more reliably than the ones implemented using classical CMOS. Although many research papers have been focused lately on using ST design concepts for implementing more reliable static random access memory (SRAM) cells, significantly less work was devoted to the application of ST concepts in the combinatorial logic domain. Moreover, available research on ST-based logic gates had only focused on the low-voltage/power applications range. The authors are going to look at the whole voltage range and performance spectrum to compare and understand not only the SNMs and the power consumption (at different frequencies and voltage levels) but also the delay and the power-delay-product of ST-based logic gates. These will be compared with classical CMOS as well as with optimally sized CMOS and ST-based logic gates. This study should give a clear picture of the potential advantages ST could offer for combinatorial logic in advanced CMOS technology nodes and of their application range.

Inspec keywords: integrated circuit design; logic gates; low-power electronics; logic design; trigger circuits; CMOS logic circuits; integrated circuit reliability; SRAM chips

Other keywords: ST-based logic gates; ST hysteresis; design static noise margin; noise stable operation; ST design concepts; low-voltage-power applications; classical CMOS gates; classical complementary metal-oxide-semiconductor gates; power consumption; power-delay-product; performance spectrum; reliability; advanced CMOS technology nodes; ST-based circuits; optimised Schmitt trigger gates; positive feedback transistors; reliable SRAM cells; combinatorial logic domain

Subjects: Logic circuits; Logic and switching circuits; Logic design methods; Semiconductor storage; Semiconductor integrated circuit design, layout, modelling and testing; CMOS integrated circuits; Memory circuits; Digital circuit design, modelling and testing; Reliability; Logic elements

References

    1. 1)
      • 44. Chen, Y.-N., Hsieh, C.-Y., Fan, M.-L., et al: ‘Impacts of intrinsic device variations on the stability of FinFET subthreshold SRAMs’. Proc. Int. Conf. IC Design and Technology (ICICDT'11), Kaohsiung, Taiwan, 2011, art. 5783210, pp. 14.
    2. 2)
      • 15. Kuo, W., Rajendra Prasad, V., Tillman, F. A., et al: ‘Optimal reliability design: fundamental and applications’ (Cambridge University Press, Cambridge, UK, 2001).
    3. 3)
      • 52. Filanovsky, I., Baltes, H.: ‘CMOS Schmitt trigger design’, IEEE Trans. Circ. Syst. I, 1994, 41, (1), pp. 4649.
    4. 4)
      • 2. Asenov, A.: ‘Random dopant induced threshold voltage lowering and fluctuations in sub-0.1µm MOSFET's: a 3-D ‘atomistic’ simulation study’, IEEE Trans. Electr. Dev., 1998, 45, (12), pp. 25052513.
    5. 5)
      • 12. Roy, S., Beiu, V.: ‘Multiplexing schemes for cost-effective fault-tolerance’. Proc. Int. IEEE Conf. Nanotechnology (IEEE-NANO'04), Munich, Germany, 2004, pp. 589592.
    6. 6)
      • 9. Wakerly, J. F.: ‘Microcomputer reliability improvement using triple-modular redundancy’, Proc. IEEE, 1976, 64, (6), pp. 889895.
    7. 7)
      • 10. Hamamatsu, M., Tsuchiya, T., Kikuno, T.: ‘On the reliability of cascaded TMR systems’. Proc. Pacific Rim Int. Symp. Dependable Computing (PRDC'10), Tokyo, Japan, 2010, pp. 184190.
    8. 8)
      • 29. Tryon, J. G.: ‘Quadded logic’, in Wilcox, R. H., Mann, W. C., (Eds.): ‘Redundancy techniques for computing systems’ (Spartan Books, Washington, DC, USA, 1962), pp. 205228.
    9. 9)
      • 7. Giustolisi, G., Palumbo, G., Criscione, M., et al: ‘A low-voltage low-power voltage reference based on subthreshold MOSFETs’, IEEE J. Solid-State Circ., 2003, 38, (1), pp. 151154.
    10. 10)
      • 23. Schmid, A., Leblebici, Y.: ‘Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors’, IEEE Trans. VLSI Syst., 2004, 12, pp. 11561166.
    11. 11)
      • 61. Ibrahim, W., Beg, A., Beiu, V.: ‘Highly reliable and low-power full adder cell’. Proc. Int. IEEE Conf. Nanotechnology (IEEE-NANO'11), Portland, OR, USA, 2011, pp. 500503.
    12. 12)
      • 63. Beiu, V., Iordaconiu, L., Beg, A., et al: ‘Low power and highly reliable gates using arrays of optimally sized transistors’. Proc. Int. Semiconductor Conf. (CAS'12), Sinaia, Romania, 2012b, pp. 433436.
    13. 13)
      • 1. Hagiwara, T., Yamaguchi, K., Shojiro, A.: ‘Threshold voltage deviation in very small MOS transistors due to local impurity fluctuations’. Proc. Int. Symp. VLSI Technology (VLSIT'82), Oiso, Japan, pp. 4647.
    14. 14)
      • 36. Martorell, F., Rubio, A.: ‘Cell architecture for nanoelectronic design’, Microelectr. J., 2008, 39, (8), pp. 10411050.
    15. 15)
      • 57. Donato, M., Cremona, F., Jin, W., et al: ‘A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic’. Proc. Great Lakes Symp. VLSI (GLSVLSI'12), Salt Lake City, UT, USA, May 2012, pp. 3944.
    16. 16)
      • 71. Hanson, S., Seok, M., Sylvester, D., et al: ‘Nanometer device scaling in subthreshold logic and SRAM’, IEEE Trans. Electr. Dev., 2008, 55, (1), pp. 175185.
    17. 17)
      • 30. Anghel, L., Nicolaidis, M.: ‘Defects tolerant logic gates for unreliable future nanotechnologies’. Proc. Intl. Work Conf. Artificial Neural Nets (IWANN'07), San Sebastián, Spain, June 2007, pp. 422429.
    18. 18)
      • 11. von Neumann, J.: ‘Probabilistic logics and the synthesis of reliable organisms from unreliable components’, in Shannon, C. E., McCarthy, J., (Eds.): ‘Automata studies’ (Princeton University Press, Princeton, NJ, USA, 1956), pp. 4398.
    19. 19)
      • 68. Zhao, W., Cao, Y.: ‘New generation of predictive technology model for sub-45 nm early design exploration’, IEEE Trans. Electr. Dev., 2006, 53, (11), pp. 28162823.
    20. 20)
      • 34. Wang, T., Bennaser, M., Guo, Y., et al: ‘Combining circuit level and system level techniques for defect-tolerant architectures’. Proc. Intl. Workshop on Defect and Fault Tolerant Nanoscale Architecture (NanoArch'06), Boston, MA, USA, Jun. 2006.
    21. 21)
      • 46. Hsieh, C.-Y., Fan, M.-L., Hu, V. P.-H., et al: ‘Independently-controlled-gate FinFET Schmitt trigger sub-threshold SRAMs’, IEEE Trans. VLSI Syst., 2012, 20, (7), pp. 12011210.
    22. 22)
      • 54. Marzaki, A., Bidal, V., Laffont, R.: ‘Wenceslas Rahajandraibe, Jean-Michel Portal, and Rashid Bouchakour. A new adjustable Schmitt trigger based on dual control gate-floating gate transistor (DCG-FGT)’. Proc. Mid-West Symp. Circuits and Systems (MWSCAS'12), Boise, ID, USA, 2012, pp. 643645.
    23. 23)
      • 24. Aunet, S., Hartmann, M.: ‘Real-time reconfigurable linear threshold elements and some applications to neural hardware’. Proc. Int. Conf. Evolvable System (ICES'03), Trondheim, Norway, Mar. 2003, pp. 365376.
    24. 24)
      • 22. Schmid, A., Leblebici, Y.: ‘Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors’. Proc. Int. IEEE Conf. Nanotechnogoy (IEEE-NANO'03), San Francisco, CA, USA, Aug. 2003, vol. 2, pp. 516519.
    25. 25)
      • 55. Yuan, F.: ‘Differential CMOS Schmitt trigger with tunable hysteresis’, Analog Integ. Circ. Signal, 2010, 62, (2), pp. 245248.
    26. 26)
      • 28. Granhaug, K., Aunet, S.: ‘Improving yield and defect tolerance in subthreshold CMOS through output-wired redundancy’, J. Electr. Test., 2008, 24, (1–3), pp. 157163.
    27. 27)
      • 19. Baze, M. P., Buchner, S. P., McMorrow, D.: ‘A digital CMOS design technique for SEU hardening’, IEEE Trans. Nuclear Sci., 2000, 47, (6), pp. 26032608.
    28. 28)
      • 37. Flak, J., Laiho, M., Paasio, A.: ‘Fault-tolerant architecture for nanoelectronics digital logic’. Proc. Intl. Conf. Signal & Electrical Systems (ICSES'08), Krakow, Poland, September 2008, pp. 545548.
    29. 29)
      • 26. Aunet, S., Berg, Y., Beiu, V.: ‘Ultra low power redundant logic based on majority-3 gates’. Proc. IFIP Int. Conf. VLSI System on Chip (VLSI-SoC'05), Perth, Australia, October 2005, pp. 553558.
    30. 30)
      • 21. Tatapudi, S., Beiu, V.: ‘Split-precharge differential noise-immune threshold logic gate (SPD-NTL)’. Proc. Int. Work-Conf. Artificial Neural Networks (IWANN'03), Menorca, Spain, Springer, LNCS 2687, Jun. 2003, pp. 4956.
    31. 31)
      • 62. Beiu, V., Beg, A., Ibrahim, W.: ‘Atto-Joule gates for the whole voltage range’. Proc. Int. IEEE Conf. Nanotechnology (IEEE-NANO'11), Portland, OR, USA, 2011, pp. 14241429.
    32. 32)
      • 4. Asenov, A.: ‘Statistical device variability and its impact on design’. IEEE Int. Symp. Asynchronous Circuits and Systems, Newcastle, UK, Apr. 2008, pp. xvxvi.
    33. 33)
      • 38. Flak, J., Laiho, M.: ‘Fault-tolerant programmable logic array for nanoelectronics’, Int. J. Circ. Theory Appl., 2012, 40, (12), pp. 12331247.
    34. 34)
      • 25. Aunet, S., Beiu, V.: ‘Ultra low power fault tolerant neural inspired CMOS logic’. Proc. Int. Joint Conf. Neural Networks (IJCNN'05), Montreal, Canada, Aug. 2005, pp. 28432848.
    35. 35)
      • 58. Gupta, P., Kahng, A. B., Sharma, P., et al: ‘Selective gate-length biasing for cost-effective runtime leakage control’. Proc. Design Automation Conf. (DAC'04), San Diego, CA, USA, 2004, pp. 327330.
    36. 36)
      • 56. Rashid, H., Mamun Ibne Reaz, M., Syedul Amin, M., et al: ‘Design of a low voltage Schmitt trigger in 0.18 µm CMOS process with tunable hysteresis’, Mod. Appl. Sci., 2013, 7, (4), pp. 4755.
    37. 37)
      • 66. Ibrahim, W., Beiu, V.: ‘Using Bayesian networks to accurately calculate the reliability of complementary metal oxide semiconductor gates’, IEEE Trans. Reliab., 2011, 60, (3), pp. 538549.
    38. 38)
      • 8. Marković, D., Wang, C. C., Alarcón, L. P., et al: ‘Ultralow-power design in near-threshold region’, Proc. IEEE, 2010, 98, (2), pp. 237252.
    39. 39)
      • 32. El-Maleh, A. H., Al-Hashimi, B. M., Melouki, A.: ‘Transistor-level based defect tolerance for reliable nanoelectronics’. Proc. Intl. Conf. Computer Systems Applications. (AICCSA'08), Doha, Qatar, Mar. 2008, pp. 5360.
    40. 40)
      • 39. Hauser, J. R.: ‘Noise margin criteria for digital logic circuits’, IEEE Trans. Edu., 1993, 36, (4), pp. 363368.
    41. 41)
      • 18. Bolchini, C., Buonanno, G., Sciuto, D., et al: ‘An improved fault tolerant architecture at CMOS level’. Proc. Int. Symp. Circulatory System (ISCAS'97), Kowloon, Hong Kong, June 1997, pp. 27372740.
    42. 42)
      • 17. Bolchini, C., Buonanno, G., Sciuto, D., et al: ‘Static redundancy techniques for CMOS gates’. Proc. Int. Symp. Circulatory System (ISCAS'96), Atlanta, GA, USA, May 1996, pp. 576579.
    43. 43)
      • 72. Zavyalova, L., Lucas, K., Zhang, Q., et al: ‘Analysis of OPC optical model accuracy with detailed scanner information’. Proc. SPIE 6924: Optical Microlithography XXI, San Jose, CA, USA, 2008, art. 69241D, pp. 112.
    44. 44)
      • 42. Morimura, H., Shimannura, T., Fujii, K., et al: ‘A zero-sink-current Schmitt trigger and window-flexible counting circuit for fingerprint sensor/identifier’. Proc. Int. Solid-State Circuits Conf. (ISSCC'04), San Fransisco, CA, USA, 2004, vol. 122–124, pp. 511517.
    45. 45)
      • 6. Soeleman, H., Roy, K.: ‘Ultra-low power digital subthreshold logic circuits’. Proc. Int. Symp. Low Power Electronics and Design, San Diego, CA, USA, 1999, pp. 9496.
    46. 46)
      • 59. Gupta, P., Kahng, A. B.: ‘Gate-length biasing for circuit optimization’. US Patent 8127266, February 28, 2012.
    47. 47)
      • 47. Lotze, N., Manoli, Y.: ‘A 62 mV 0.13 µm CMOS standard-cell-based design technique using Schmitt-trigger logic’, IEEE J. Solid-State Circ., 2011, 47, (1), pp. 4760.
    48. 48)
      • 70. Berkeley Short-channel IGFET Model (BSIM4.8.0). 2013. Available at: http://bsim.berkeley.edu/models/bsim4/.
    49. 49)
      • 69. Zhao, W., Cao, Y.: ‘Predictive technology model for nano-CMOS design exploration’, ACM J. Emerg. Technol. Comput. Syst., 2007, 3, (1), pp. 117.
    50. 50)
      • 67. Predictive Technology Model (PTM). Available at: http://ptm.asu.edu/.
    51. 51)
      • 35. Chen, C.: ‘Reliability-driven gate replication for nanometer-scale digital logic’, IEEE Trans. Nanotechnol., 2007, 6, (3), pp. 303308.
    52. 52)
      • 20. Beiu, V.: ‘Ultra-fast noise immune CMOS threshold gates’. Proc. Int. Midwest Symp. Circulatory System (MWSCAS'00), Lansing, MI, USA, August 2000, pp. 13101313.
    53. 53)
      • 45. Kulkarni, J. P., Roy, K.: ‘Ultralow voltage process variation tolerant Schmitt trigger based SRAM design’, IEEE Trans. VLSI, 2012, 20, (2), pp. 319332.
    54. 54)
      • 49. Beiu, V., Beg, A., Ibrahim, W., et al: ‘Enabling sizing for enhancing the static noise margins’. Proc. Int. Symp. Quality Electronic Design (ISQED'13), Santa Clara, CA, USA, 2013, pp. 278285.
    55. 55)
      • 16. Bolchini, C., Buonanno, G., Sciuto, D., et al: ‘A CMOS fault tolerant architecture for switch-level faults’. Proc. Int. Workshop Defect & Fault Tolerance VLSI System (DFT'94), Montreal, Canada, October 1994, pp. 1018.
    56. 56)
      • 64. Beiu, V., Tache, M., Ibrahim, W., et al: ‘On upsizing length and noise margins’. Proc. Int. Semiconductor Conf. (CAS'13), Sinaia, Romania, 2013, pp. 219222.
    57. 57)
      • 31. Djupdal, A., Haddow, P. C.: ‘Defect tolerant ganged CMOS minority gate’. Proc. NORCHIP'07, Aalborg, Denmark, Novemberr 2007, art. 4481060, pp. 14.
    58. 58)
      • 51. Dokić, B. L.: ‘CMOS Schmitt triggers’, IEE Proc. Part G, 1984, 131, (5), pp. 197202.
    59. 59)
      • 40. Schmitt, O. H.: ‘A thermionic trigger’, J. Sci. Instrum., 1938, 15, (1), pp. 2426.
    60. 60)
      • 43. Kim, H., Kim, H.-J., Chung, W.-S.: ‘Pulse width modulation circuits using CMOS OTAs’, IEEE Trans. Circ. Syst. I, 2007, 54, (9), pp. 18691878.
    61. 61)
      • 48. Ibrahim, W., Beiu, V., Beg, A.: ‘Optimum reliability sizing for complementary metal oxide semiconductor gates’, IEEE Trans. Reliab., 2012, 61, (3), pp. 675686.
    62. 62)
      • 27. Granhaug, K., Aunet, S.: ‘Improving yield and defect tolerance in multifunction subthreshold CMOS gates’. Proc. Int. Symp. Defect & Fault-Tolerance VLSI System (DFT'06), Arlington, VA, USA, Oct. 2006, pp. 2028.
    63. 63)
      • 60. Beiu, V., Beg, A., Ibrahim, W., et al: ‘Towards ultra-low power/voltage using unconventionally sized arrays of transistors’. Proc. Int. IEEE Conf. Nanotechnology (IEEE-NANO'12), Birmingham, UK, 2012a, art. 6322071, pp. 15.
    64. 64)
      • 13. Roy, S., Beiu, V.: ‘Majority multiplexing — economical redundant fault-tolerant design for nano architectures’, IEEE Trans. Nanotechnol., 2005, 4, (4), pp. 441451.
    65. 65)
      • 73. Lohstroh, J.: ‘Static and dynamic noise margins of logic circuits’, IEEE J. Solid-State Circ., 1979, 14, (3), pp. 591598.
    66. 66)
      • 53. Zhang, C., Srivastava, A., Ajmera, P. K.: ‘Low voltage CMOS Schmitt trigger circuits’, IEE Electr. Lett., 2003, 39, (24), pp. 16961698.
    67. 67)
      • 65. Tache, M., Beiu, V., Ibrahim, W., et al: ‘Sizing for static noise margins revisited’. Proc. European Workshop on CMOS Variability (VARI'13), Karlsruhe, Germany, 2013, in press.
    68. 68)
      • 3. Asenov, A., Brown, A.R., Davies, J.H., et al: ‘Simulation of intrinsic parameter fluctuations in decanometer and nanometer-scale MOSFETs’, IEEE Trans. Electr. Dev., 2003, 50, (5), pp. 18371852.
    69. 69)
      • 41. Ikeda, N.: ‘Schmitt trigger input buffer circuit’. US Patent 5327020, July 5, 1994.
    70. 70)
      • 14. Sadek, A. S., Nikolić, K., Forshaw, M.: ‘Parallel information and computation with restitution for noise-tolerant nanoscale logic networks’, Nanotechnology, 2004, 15, (1), pp. 192210.
    71. 71)
      • 33. Moritz, C. A., Wang, T.: ‘Towards defect-tolerant nanoscale architectures’. Proc. IEEE Conf. Nanotechnology (IEEE-NANO'06), Cincinnati, OH, USA, Jul. 2006, pp. 331334.
    72. 72)
      • 5. Intl. Tech. Roadmap for Semiconductors (ITRS) 2.0, SEMATECH, Albany, NY, USA, 2015. Available at http://www.itrs2.net/.
    73. 73)
      • 50. Dokić, B. L.: ‘CMOS regenerative logic circuits’, Microelectr. J., 1983, 14, (5), pp. 2130.
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