Through silicon via (TSV) interconnect reliability is a problem in electronic packaging. The authors address the insertion losses, deflections which can result to separation of TSV layers and hoop stresses. These problems are due to different coefficient of thermal expansion between materials. The authors propose a robust methodology for (TSV) liners in this paper which in turn solves the reliability problem in (TSV). Silicon dioxide material is used in their paper as a TSV liner. First, they modelled the equivalent TSV circuit in advanced design systems (ADS). The authors then simulated it to obtain the TSV characterisation from which they obtained the S-parameter S21 which represents the insertion losses. Insertion losses have been described with changes in frequencies from 0 to 20 GHz with changes in TSV thickness from 7 to 8 µm. Later two different shapes of the TSV liner; the disc- and rod-shaped are modelled in analysis system 14 software. The two shapes with a radius of 5 µm each and a fixed pressure of 100 µPa developed changes in hoop stresses and deflections when the liners thicknesses are varied from 2 to 3 µm. The disc shape experienced least reliability problems so the authors propose its use in via structures.

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Effects of varying the through silicon via liners thickness on their hoop stresses and deflections

References

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