http://iet.metastore.ingenta.com
1887

access icon openaccess Effects of varying the through silicon via liners thickness on their hoop stresses and deflections

Loading full text...

Full text loading...

/deliver/fulltext/joe/2017/4/JOE.2017.0019.html;jsessionid=1fy8uwr6e1c1k.x-iet-live-01?itemId=%2fcontent%2fjournals%2f10.1049%2fjoe.2017.0019&mimeType=html&fmt=ahah

References

    1. 1)
    2. 2)
      • 2. Gao, X., Chen, R., Wang, X., et al: ‘Thermo-mechanical reliability of copper-filled and polymer-filled through silicon vias in 3d interconnects’. 2013 IEEE 63rd Electronic Components and Technology Conf. (ECTC), 2013, pp. 21322137.
    3. 3)
      • 3. Reddy, R.R., Tanna, S., Singh, S.G., et al: ‘TSV noise coupling in 3D IC using guard ring’. 2015 Int. 3D Systems Integration Conf. (3DIC), Sendai, 2015, pp. TS8.35.1TS8.35.5.
    4. 4)
      • 4. Bandyopadhyay, T., Chatterjee, R., Chung, D., et al: ‘Electrical modeling of through silicon and package vias’. IEEE Int. Conf. on 3D System Integration, 2009. 3DIC 2009, 2009, pp. 18.
    5. 5)
    6. 6)
    7. 7)
    8. 8)
      • 8. Harrison, E.A., Abbott, C.: ‘The title of the book’ (XYZ Press, 2005, 2nd edn. 2006).
    9. 9)
    10. 10)
      • 10. Liu, F., Yu, R.R., Young, A.M., et al: ‘A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding’. IEEE Int. Electron Devices Meeting, 2008. IEDM 2008, 2008, pp. 14.
    11. 11)
      • 11. Weerasekera, R., Grange, M., Pamunuwa, D., et al: ‘Compact modelling of through-silicon vias (tsvs) in three-dimensional (3d) integrated circuits’. IEEE Int. Conf. on 3D System Integration, 2009. 3DIC 2009, 2009, pp. 18.
    12. 12)
      • 12. Liu, C., Song, T., Cho, J., et al: ‘Full-chip TSV-TOTSV coupling analysis and optimization in 3d IC’. 2011 48th ACM/EDAC/IEEE Design Automation Conf. (DAC), 2011, pp. 783788.
    13. 13)
      • 13. Cao, Y., Xia, Z., Li, Q., et al: ‘Electret properties of silicon dioxide aerogels’. Ninth Int. Symp. on Electrets, 1996 (ISE 9), 1996, pp. 4045.
    14. 14)
    15. 15)
    16. 16)
      • 16. Tezcan, D.S., Duval, F., Philipsen, H., et al: ‘Scalable through silicon via with polymer deep trench isolation for 3d wafer level packaging’. 59th Electronic Components and Technology Conf., 2009. ECTC 2009, 2009, pp. 11591164.
    17. 17)
    18. 18)
    19. 19)
    20. 20)
      • 20. Civale, Y., Croes, K., Miyamori, Y., et al: ‘Thermal stability of copper through-silicon via barriers during IC processing’. 2011 IEEE Int. Interconnect Technology Conf. and 2011 Materials for Advanced Metallization (IITC/MAM), , 2011, pp. 13.
    21. 21)
      • 21. Chen, Z., Song, X., Liu, S.: ‘Thermo-mechanical characterization of copper filled and polymer filled TSVS considering nonlinear material behaviors’. 59th Electronic Components and Technology Conf., 2009. ECTC 2009, 2009, pp. 13741380.
    22. 22)
      • 22. Suhir, E.: ‘Analytical stress modeling for TSVS in 3d packaging’. 31st Thermal Measurement, Modeling Management Symp. (SEMI-THERM), 2015, 2015, pp. 99106.
    23. 23)
      • 23. Yoo, K., Lee, S., Kim, J.: ‘A central axis and radius estimation method for torus object modeling’. IEEE Int. Symp. on Assembly and Manufacturing (ISAM), 2011, 2011, pp. 16.
    24. 24)
      • 24. Suhir, E., Savastiouk, S.: ‘Disc-like copper vias fabricated in a silicon wafer: design for reliability’. 58th Electronic Components and Technology Conf., 2008. ECTC 2008., 2008, pp. 16641666.
    25. 25)
      • 25. Witarsa, D., Soundarapandian, M., Yoon, S.W., et al: ‘Through wafer copper via for silicon based sip application’. Proc. of Seventh Electronic Packaging Technology Conf., 2005. EPTC 2005, 2005, vol. 1, p. 6.
    26. 26)
      • 26. Okoro, C., Gonzalez, M., Vandevelde, B., et al: ‘Prediction of the influence of induced stresses in silicon on CMOS performance in a Cu-through-via interconnect technology’. Int. Conf. on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems, 2007. EuroSime 2007, 2007, pp. 17.
    27. 27)
      • 27. Tanaka, N., Sato, T., Yamaji, Y., et al: ‘Mechanical effects of copper through-vias in a 3d die-stacked module’. Proc. 52nd Electronic Components and Technology Conf., 2002, 2002, pp. 473479.
    28. 28)
      • 28. Worwag, W., Dory, T.: ‘Copper via plating in three dimensional interconnects’. Proc. 57th Electronic Components and Technology Conf., 2007. ECTC ‘07, 2007, pp. 842846.
    29. 29)
      • 29. Laviron, C., Dunne, B., Lapras, V., et al: ‘Via first approach optimisation for through silicon via applications’. 59th Electronic Components and Technology Conf., 2009. ECTC 2009, 2009, pp. 1419.
http://iet.metastore.ingenta.com/content/journals/10.1049/joe.2017.0019
Loading

Related content

content/journals/10.1049/joe.2017.0019
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address