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access icon openaccess Particle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis

This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)
Received 05/01/2017, Accepted 19/04/2017, Published 28/04/2017

Owing to aggressive shrinking in nanometre scale as well as faster devices, particle strike manifesting itself into transient fault spanning multiple cycle and multiple units will be the centre-focus of application specific datapath generated through high-level synthesis (HLS)/architectural synthesis. Addressing each problem above separately leads to large area/delay overhead; thus tackling both problems concurrently, leads to huge incurred overhead. To tackle this complex problem, this paper proposes a novel low cost particle swarm optimisation driven dual modular redundant (DMR) based HLS methodology for generation of a transient fault secured design secured against its temporal and spatial effects. The authors' approach provides a low cost optimised fault secured solution through a particle swarm optimisation exploration framework based on user area-delay constraints. Results indicated that proposed approach obtains an area overhead reduction of 34.08% and latency overhead reduction of 5.8% compared with a recent approach.

Inspec keywords: particle swarm optimisation; high level synthesis

Other keywords: dual modular redundant; area/delay overhead; architectural synthesis; area-delay constraints; low-cost single event transient fault secured design; particle swarm optimisation; application specific datapath; high-level synthesis; DMR

Subjects: Optimisation techniques; Computer-aided circuit analysis and design; Computer-aided logic design; Optimisation techniques

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