This is an open access article published by the IET under the Creative Commons Attribution -NonCommercial License (http://creativecommons.org/licenses/by-nc/3.0/)
This study presents a high-speed signed Vedic multiplier (SVM) architecture using redundant binary (RB) representation in Urdhva Tiryagbhyam (UT) sutra. This is the first ever effort towards extension of Vedic algorithms to the signed numbers. The proposed multiplier architecture solves the carry propagation issue in UT sutra, as carry free addition is possible in RB representation. The proposed design is coded in VHDL and synthesised in Xilinx ISE 14.4 of various FPGA devices. The proposed SVM architecture has better speed performances as compared with various state-of-the-art conventional as well as Vedic architectures.
References
-
-
1)
-
2. Booth, A.D.: ‘A signed binary multiplication technique’, Q. J. Mech. Appl. Math., 1951, 4, (2), pp. 236–240 (doi: 10.1093/qjmam/4.2.236).
-
2)
-
3. Wallace, C.S.: ‘A suggestion for a fast multiplier’, IEEE Trans. Electron. Comput., 1964, (1), pp. 14–17.
-
3)
-
19. Kodali, R.K., Boppana, L., Yenamachintala, S.S.: ‘FPGA implementation of vedic floating point multiplier’. Signal Processing, Informatics, Communication and Energy Systems (SPICES), 2015 IEEE Int. Conf. on IEEE, 2015, pp. 1–4.
-
4)
-
18. Saha, P., Banerjee, A., Dandapat, A., Bhattacharyya, P.: ‘ASIC design of a high speed low power circuit for calculation of factorial of 4-bit numbers based on ancient vedic mathematics’, Microelectron. J. (Elsevier), 2011, 42, (12), pp. 1343–1352 (doi: 10.1016/j.mejo.2011.09.001).
-
5)
-
18. Saha, P., Banerjee, A., Bhattacharyya, P., et al: ‘High speed ASIC design of complex multiplier using Vedic mathematics’. ‘Students’ Technology Symp. (TechSym), 2011 IEEE IEEE, 2011, pp. 237–241.
-
6)
-
20. Kandasamy, W.B.V., Smarandache, F.: , 2006).
-
7)
-
9. Sethi, K., Panda, R.: ‘Multiplier less high-speed squaring circuit for binary numbers’, Int. J. Electron., 2015, 102, (3), pp. 433–443 (doi: 10.1080/00207217.2014.897381).
-
8)
-
7. Tirtha, S.B.K., Agrawala, V.S., Agrawala, V.S.: ‘Vedic mathematics’ (Motilal Banarsidass Publ., 1992).
-
9)
-
16. Pushpangadan, R., Sukumaran, V., Innocent, R., et al: ‘High speed vedic multiplier for digital signal processors’, IETE J. Res., 2009, 55, (6), pp. 282–286 (doi: 10.4103/0377-2063.59167).
-
10)
-
23. Xilinx, V.-I.: 2007, 28, pp. 1–502.
-
11)
-
24. UG070, U.G.: ‘Virtex-4 FPGA user guide’ (Xilinx Inc, 2008).
-
12)
-
6. Besli, N., Deshmukh, R.G.: ‘A novel redundant binary signed-digit (RBSD) Booth's encoding’. SoutheastCon, 2002. Proc. IEEE IEEE, 2002, pp. 426–431.
-
13)
-
15. Bansal, Y., Madhu, C.: ‘A novel high-speed approach for 16 × 16 Vedic multiplication with compressor adders’, Comput. Electr. Eng., 2016, 49, pp. 39–49 (doi: 10.1016/j.compeleceng.2015.11.006).
-
14)
-
12. Mehta, P., Gawali, D.: ‘Conventional versus Vedic mathematical method for hardware implementation of a multiplier’. Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT'09. Int. Conf. on IEEE, 2009, pp. 640–642.
-
15)
-
1. Parhami, B.: ‘Computer arithmetic and hardware designs’ (Oxford University Press, 2000).
-
16)
-
21. Avizienis, A.: ‘Signed-digit number representations for fast parallel arithmetic’, IRE Trans. Electron. Comput., 1961, (3), pp. 389–400.
-
17)
-
10. Pradhan, M., Panda, R.: ‘High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics’, Int. J. Electron., 2014, 101, (3), pp. 300–307 (doi: 10.1080/00207217.2013.780298).
-
18)
-
17. Ramalatha, M., Dayalan, K.D., Dharani, P., et al: ‘High speed energy efficient ALU design using vedic multiplication techniques’. Advances in Computational Tools for Engineering Applications, 2009. ACTEA'09. Int. Conf. on IEEE, 2009, pp. 600–603.
-
19)
-
13. Barik, R.K., Pradhan, M.: ‘Area-time efficient square architecture’, AMSE J., Adv. D, 2015, 20, (1), pp. 21–34.
-
20)
-
4. Hu, J., Wang, L., Xu, T.: ‘A low-power adiabatic multiplier based on modified Booth algorithm’. 2007 Int. Symp. on Integrated Circuits IEEE, 2007, pp. 489–492.
-
21)
-
14. Barik, R.K., Pradhan, M.: ‘Efficient ASIC and FPGA implementation of cube architecture’, IET Comput. Digit. Tech., 2017, 11, (1), pp. 43–49 (doi: 10.1049/iet-cdt.2016.0043).
-
22)
-
22. Pedroni, V.A.: ‘Circuit design with VHDL’ (MIT press, 2004).
-
23)
-
8. Kasliwal, P.S., Patil, B.P., Gautam, D.K.: ‘Performance evaluation of squaring operation by Vedic mathematics’, IETE J. Res., 2011, 57, (1), pp. 39–41 (doi: 10.4103/0377-2063.78327).
-
24)
-
5. Kuang, S.-R., Wang, J.-P., Guo, C.-Y.: ‘Modified booth multipliers with a regular partial product array’, IEEE Trans. Circuits Syst. II Express Briefs, 2009, 56, (5), pp. 404–408 (doi: 10.1109/TCSII.2009.2019334).
http://iet.metastore.ingenta.com/content/journals/10.1049/joe.2016.0376
Related content
content/journals/10.1049/joe.2016.0376
pub_keyword,iet_inspecKeyword,pub_concept
6
6