http://iet.metastore.ingenta.com
1887

access icon openaccess Vedic division methodology for high-speed very large scale integration applications

Loading full text...

Full text loading...

/deliver/fulltext/joe/2014/2/JOE.2013.0213.html;jsessionid=1124kffd4eakv.x-iet-live-01?itemId=%2fcontent%2fjournals%2f10.1049%2fjoe.2013.0213&mimeType=html&fmt=ahah

References

    1. 1)
      • 1. Juang, T.-B., Chen, S.-H.H., Li, S.M.: ‘A novel VLSI iterative divider architecture for fast quotient generation’. Proc. IEEE Int. Symp. Circuits and Systems 2011, Seattle, WA, USA, May 2008, pp. 33583361.
    2. 2)
    3. 3)
      • 3. Deschamps, J.-P., Bioul, G.J.A., Sutter, G.D.: ‘Synthesis of arithmetic circuits, FPGA, ASIC and embedded system’ (John Wiley & Sons, Inc., 2006).
    4. 4)
      • 4. Hagglund, R., Lowenborg, P., Vesterbacka, M.: ‘A polynomial-based division algorithm’, Proc. IEEE Int. Symp. Circuits Syst., 2002, 3, pp. 571574.
    5. 5)
      • 5. Aggarwal, N., Asooja, K., Verma, S.S., Negi, S.: ‘An improvement in the restoring division algorithm (needy restoring division algorithm)’. Proc. IEEE Int. Conf. Computer Science and Information Technology, Beijing, August 2009, pp. 246249.
    6. 6)
      • 6. Sutter, G., Deschamps, J.P.: ‘High speed fixed point divider for FPGAS’. Proc. IEEE Int. Conf. Field Programmable Logic and Applications, Prague, August 2009, pp. 448452.
    7. 7)
      • 7. Sutter, G., Deschamps, J.P.: ‘Fast radix 2k divider for FPGAs’. Proc. IEEE Int. Conf. Programmable Logic, Sao Carlos, April 2009, pp. 115122.
    8. 8)
      • 8. Jun, K., Swartzlander, E.E.Jr.: ‘Modified non-restoring division algorithm with improved delay profile and error correction’. Proc. IEEE Int. Conf. Signals System and Computer, 2012, pp. 14601464.
    9. 9)
    10. 10)
      • 10. Louvet, N., Muller, J.M., Panhaleux, A.: ‘Newton–Raphson algorithms for floating-point division using an FMA’. Proc. IEEE Int. Conf. Application Specific Systems Architectures and Processors, Rennes, France, July 2010, pp. 200207.
    11. 11)
      • 11. Piso, D., Bruguera, J.D.: ‘Simplifying the rounding for Newton–Raphson algorithm with parallel remainder’. Proc. IEEE Int. Conf. Signals Systems and Computers, Pacific Grove, CA, USA, November 2009, pp. 921925.
    12. 12)
      • 12. Nenadic, N.M., Mladenovic, S.B.: ‘Fast division on fixed-point DSP processors using Newton–Raphson method’. Proc. IEEE Int. Conf. Computers as a Tool, Belgrade, November 2005, pp. 705708.
    13. 13)
      • 13. Guy, E., Seidel, P.-M.M., Warren, E.F.Jr.: ‘A parametric error analysis of Goldschmidt's division algorithm’. Proc. IEEE Int. Conf. Computer Arithmetic, June 2003, pp. 165171.
    14. 14)
    15. 15)
    16. 16)
      • 16. Maharaja, J.S.S.B.K.T.: ‘Vedic mathematics’ (Motilal Banarsidass Publishers Pvt Ltd, Delhi, 2001).
    17. 17)
      • 17. Saha, P., Banerjee, A., Bhattacharyya, P., Dandapat, A.: ‘Vedic divider: novel architecture (ASIC) for high speed VLSI applications’. Proc. IEEE Int. Symp. System Design, Kochi, India, December 2011, pp. 6771.
    18. 18)
    19. 19)
      • 19. Uyemura, J.P.: ‘CMOS logic circuit design’ (Kluwer Academic Publishers, 2001).
    20. 20)
http://iet.metastore.ingenta.com/content/journals/10.1049/joe.2013.0213
Loading

Related content

content/journals/10.1049/joe.2013.0213
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address