Adaptive progressive thresholding (APT) has been shown to be an efficient method to segment the lumen region of endoscopic images. A pipelined architecture was previously proposed in an attempt to accelerate the conventional APT in hardware. In the paper, a novel architecture for the between-class variance computations of APT is presented to minimise the severe bottleneck of the iterative loop in the APT process. The technique employs binary logarithm conversion to eliminate the computationally intensive dividers and reduce the complexity of the multipliers of the previous architecture. The proposed method employs a re-configurable logarithmic computing unit, which can be configured to achieve a highly accurate between-class variance unit. It has been shown that the proposed approach leads to area–time efficient FPGA implementation which is capable of a computation speed-up of ∼2.75 times while occupying only one-sixth of the number of slices required by the previous approach.
