Your browser does not support JavaScript!

Novel FPGA implementations of Walsh–Hadamard transforms for signal processing

Novel FPGA implementations of Walsh–Hadamard transforms for signal processing

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IEE Proceedings - Vision, Image and Signal Processing — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The paper describes two approaches suitable for a field-programmable gate-array (FPGA) implementation of fast Walsh–Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both a systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh–Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both a distributed arithmetic ROM and accumulator structure, and a sparse matrix-factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.


    1. 1)
      • AMIRA, A., BOURIDANE, A., MILLIGAN, P., SAGE, P.: `A high throughput, FPGA implementation of a bit-level matrix product', Proceedings of the IEEE Workshop on Signal processing systems design and implementation (SIPS), 2000, LA, USA, p. 356–364.
    2. 2)
      • S.Y. Kung . (1988) , VLSI array processors.
    3. 3)
      • K.P. LIM , A. PREMKUMAR . A modular approach to the computation of convolution sum using distributed arithmetic principles. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , 1 , 92 - 96
    4. 4)
      • AMIRA, A., BOURIDANE, A., MILLIGAN, P.: `A novel architecture for Walsh–Hadamard transforms using distributed arithmetic principles', Proceedings of the 7th IEEE International Conference on Electronics, circuits & systems (ICECS'2K), 2000, 1, Beirut, Lebanon, p. 182–185.
    5. 5)
      • S. NAYAK , P. MEHER . High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , 5 , 655 - 658
    6. 6)
      • K. PARHI . (1999) , VLSI digital signal processing systems design and implementation.
    7. 7)
      • T.-S. CHANG , C. CHEN , C.-W. JEN . New distributed arithmetic algorithm and its application to IDCT. IEE Proc., Circuit Devices Syst. , 4 , 159 - 163
    8. 8)
      • D. COPPERSMITH , E. FEIG , E. LINZER . Hadamard transforms on multiply/add architecture. IEEE Trans. Signal Process. , 4 , 969 - 970
    9. 9)
      • AMIRA, A., BOURIDANE, A., MILLIGAN, P.: `RCMAT: a reconfigurable coprocessor for matrix algorithms', Proceedings of the 9th ACM International Symposium on Field-programmable gate arrays (FPGA 2001), Monterey, 2001, CA, USA, p. 228.
    10. 10)
      • L. CHANG , M. CHANG . A bit level systolic array for Walsh–Hadamard transforms. Signal Process. , 341 - 347
    11. 11)
      • S. RAHARDJA , B.J. FALKOWSKI . Family of unified complex Hadamard transforms. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , 8 , 1094 - 1100
    12. 12)

Related content

This is a required field
Please enter a valid email address