Design methodology for construction of asynchronous pipelines with Handel-C
Design methodology for construction of asynchronous pipelines with Handel-C
- Author(s): R.P. Self ; M. Fleury ; A.C. Downton
- DOI: 10.1049/ip-sen:20030206
For access to this article, please select a purchase option:
Buy article PDF
Buy Knowledge Pack
IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.
Thank you
Your recommendation has been sent to your librarian.
- Author(s): R.P. Self 1 ; M. Fleury 1 ; A.C. Downton 1
-
-
View affiliations
-
Affiliations:
1: Department of Electronic Systems Engineering, University of Essex, Wivenhoe Park, UK
-
Affiliations:
1: Department of Electronic Systems Engineering, University of Essex, Wivenhoe Park, UK
- Source:
Volume 150, Issue 1,
February 2003,
p.
39 – 47
DOI: 10.1049/ip-sen:20030206 , Print ISSN 1462-5970, Online ISSN 1463-9831
CSP channels are proposed as a means of developing high-level, asynchronous pipeline architectures over and above existing synchronous logic. Channel-based design allows hardware systems to be designed and constructed using top-down software engineering methods, which have not previously been available within hardware–software co-design. The intention is to enhance support for future large-scale co-designs. The design methodology and its performance implications are demonstrated through an exemplar, pipelined design of the Karhunen–Loève Transform (KLT) algorithm, implemented using the Handel-C silicon compiler applied to dense FPGAs.
Inspec keywords: circuit layout CAD; hardware-software codesign; Karhunen-Loeve transforms; field programmable gate arrays; communicating sequential processes; pipeline processing; asynchronous circuits
Other keywords:
Subjects: Computer-aided circuit analysis and design; Parallel programming and algorithm theory; Parallel architecture; Logic and switching circuits; Digital circuit design, modelling and testing; Sequential switching theory; Logic circuits; Hardware-software codesign; Integral transforms; Electronic engineering computing; Engineering mathematics and numerical techniques; Integral transforms
References
-
-
1)
- M. Fleury , A.C. Downton , A.F. Clark . Karhunen-Loève transform: an exercise in simple image-processing pipelines. Comput. Artif. Intell. , 1 , 19 - 36
-
2)
- W. Wolf . (2005) Computers as components: principles of embedded computing system design.
-
3)
- Hilfinger, P.: `A high-level language and silicon compiler for digital signal processing', Proceedings of the IEEE Custom integrated circuit Conference, 1985, p. 213–216.
-
4)
- Masters, P.: ‘ACM technology guide, Chapter 1: Problems with rigid computing’, p. 27, available from http://www.qstech.com/acm_tech_guide.htm, Nov. 2002.
-
5)
- ‘Virtex-II ProTM platform FPGA handbook’, Xilinx Inc., http://www.xilinx.com/publications/products/v2pro/handbook/index.htm, 2002.
-
6)
- Snider, G., Shackleford, B., Carter, R.J.: `Attacking the semantic gap between application programming languages and configurable hardware', Proceedings of 9th International Symposium on Field programmable gate arrays, 2001, p. 115–124.
-
7)
- M. Fleury , A.C. Downton . (2001) Pipelined processor farms: structured design for embedded parallel systems.
-
8)
- Kambe, T., Yamada, A., Nishida, K., Okada, K., Ohnishi, M., Kay, A., Boca, P., Zammit, V., Nomura, T.: `A C-based synthesis system, Bach, and its applications', Proceedings of ASP-DAC, February 2001, p. 151–155.
-
9)
- K.C. Chang . (1999) Digital systems design with VHDL and synthesis: an integrated approach.
-
10)
- , : `Occam 2 reference manual', 1988.
-
11)
- I. Page . Constructing hardware-software from a single description. J. VLSI Signal Process. , 87 - 107
-
12)
- J. McCormack , R. McNamara , C. Gianos , N.P. Jouppi , T. Dutton , J. Zurawski , L. Seler , K. Correll . Implementing Neon: a 256-bit graphics accelerator. IEEE Micro , 2 , 58 - 69
-
13)
- Vanmeerbeeck, G., Schaumont, P., Vernalde, S., Engels, M., Bolsens, I.: `Hardware/software partitioning of embedded system in OCAPI-xl', Proceedings of CODES'01, April 2001, p. 25–27.
-
14)
- Hilderink, G., Broenink, J., Vervoort, W., Bakkers, A.: `Communicating Java threads', 20thWoTUG conference, 1997, p. 48–76.
-
15)
- Van Rompaey, K., Verkest, D., Bolsens, I., De Man, H.: `CoWare—a design environment for heterogeneous hardware/software systems', Proceedings of EURO-DAC'96, 1996, p. 252–257.
-
16)
- J.F. Wakerly . (2000) Digital design: principles and practice.
-
17)
- N. Nissanke . (1997) Realtime systems.
-
18)
- P. Arato , T. Visgrady , I. Jankovits . (2001) High level synthesis of pipelined datapaths.
-
19)
- C.A.R. Hoare . Communicating sequential processes. Commun. ACM , 8 , 666 - 676
-
20)
- M. Fleury , R.P. Self , A.C. Downton . Hardware compilation for software engineers: an ATM example. IEE Proc. Softw. , 1 , 31 - 42
-
21)
- A.C. Downton , R.W.S. Tregidgo , A. Çuhadar . Top-down structured parallelisation of embedded image processing applications. IEE Proc. Commun. , 6 , 431 - 437
-
22)
- Verkest, D., Kunkel, J., Schirrmeister, F.: `System-level design using C++', Proceedings of DATE'00, March 2000, p. 74–80.
-
23)
- R. Rajsuman . (2000) System-on-a-chip: design and test.
-
24)
- Liao, S.Y.: `Towards a new standard for system level design', 8thInternational workshop on Hardware/software codesign, CODES 2000, May 2000, San Diego, California, p. 2–7.
-
25)
- C. Szyperski . (2003) Component software: beyond object-oriented programming.
-
26)
- Dömer, R.: `The SpecC system-level design language and methodology, Parts 1 & 2', Embedded systems Conference, March 2002.
-
27)
- Zhu, X., Lin, B.: `Hardware compilation for FPGA-based configurable computing machines', Proceedings of DAC'99, June 1999, p. 697–702.
-
28)
- R.P. Self , M. Fleury , A.C. Downton . A run-time executive on a platform FPGA. IEEE Des. Test
-
29)
- Bowen, M.: `Handel-C language reference manual', 2001.
-
1)
Related content
