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Hardware compilation for software engineers: An ATM example

Hardware compilation for software engineers: An ATM example

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Forthcoming technology such as single-chip RISC/FPGA combinations make hardware compilation, fast prototyping and FPGA replacement of ASICs all more likely. FPGAs have made a software-oriented approach to digital design feasible. Remaining obstacles to this approach are reviewed. The trade-offs between use of an HDL and a C-variant, Handel-C, for logic synthesis are considered, particularly in regard to programmability and the overall design process. A simple example in a likely application area, simulation/emulation of telecommunications switches, illustrates the analysis.

Inspec keywords: bibliographies; field programmable gate arrays; logic CAD; circuit layout CAD; asynchronous transfer mode; hardware description languages; telecommunication computing; telecommunication switching

Other keywords: logic synthesis; software engineers; FPGA replacement; hardware compilation; software-oriented approach; digital design; C-variant; telecommunications switch simulation; Handel-C; overall design process; HDL; single-chip RISC/FPGA combinations; fast prototyping; ATM example; programmability

Subjects: Logic circuits; Computer-aided logic design; Communication switching; Communications computing; Switching centres and equipment; Formal methods; High level languages; Electronic engineering computing; Computer-aided circuit analysis and design

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