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Characterisation of inter-metal dielectric deposition processes on CMOS backplanes for liquid crystal on silicon microdisplays

Characterisation of inter-metal dielectric deposition processes on CMOS backplanes for liquid crystal on silicon microdisplays

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For optimal optical performance of a microdisplay, the degree of surface planarisation of the CMOS active matrix backplane has to be superior to that of conventional CMOS. Oxide-deposition processes have been characterised to evaluate their effectiveness in planarising microdisplay backplanes. To investigate the trench-filling capabilities of the respective oxide deposition processes, the authors prepared test samples that had a set of trench patterns (1–6 μm wide) etched into 4 μm-thick thermal oxide on a Si substrate. They found that the trench-filling capability of an electron cyclotron resonance chemical vapour deposition (ECR CVD) process is superior to that of a pyrolytic CVD process. They have investigated the effects of ECR CVD deposition parameters on trench-filling properties and demonstrated the ability to produce deposited oxide layers which fill high aspect ratio trenches without producing voids.

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