A novel microwave probing application using elastomer mesh is described. It is targeted for testing wafer level packages with very fine pitch of the order of 100 micron and large pin counts of the order of a thousand. The metallised elastomer mesh provides mechanical compliance as well as good electrical contact. A mesh-coplanar probe is modelled by the partial element equivalent circuit (PEEC) method. The model is verified through frequency domain measurements on a prototype test fixture.
References
-
-
1)
-
Deng, C., Ang, S., Feng, H.H., Tay, A.A.O., Rotaru, M., Keezer, D.: `A MEMS based interposer for nano-wafer level packaging test', Proc. Electronics Packaging Technology Conf., December 2003, p. 405–409.
-
2)
-
Jayabalan, J., Goh, C.K., Ooi, B.L., Leong, M.S., Iyer, M.K., Tay, A.A.O.: `PLL based high speed functional testing', Proc. IEEE Asian Test Symp., 2003, p. 116–119.
-
3)
-
J. Jayabalan ,
B.L. Ooi ,
W. Bin ,
X. Daoxian ,
M.K. Iyer ,
M.S. Leong
.
A methodology for accurate modeling of pad structure from S-parameter measurements.
Microw. Opt. Technol. Lett.
,
2 ,
115 -
118
-
4)
-
M. Lautner ,
G. Bieser
.
Probing ASIC devices.
Solid State Technol.
,
111 -
114
-
5)
-
P.J. Restle ,
A.E. Ruehli ,
S.G. Walker ,
G. Papadopoulos
.
Full-wave PEEC time-domain method for the modeling of on-chip interconnects.
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
,
7 ,
877 -
887
-
6)
-
I.D. Robertson
.
(1995)
MMIC design.
-
7)
-
Tada, T., Takagi, R., Nakao, S., Hyozo, M., Arakawa, T., Sawada, K., Ueda, M.: `A fine pitch probe technology for VLSI wafer testing', Proc. Int. Test Conf., 10–14 Sept. 1990, p. 900–906.
-
8)
-
Tonks, D., Vaillancourt, W., Smith, K., Strid, E.: `An application of membrane probes for on-wafer testing of unmatched high power MMICs', IEEE MTT-S Int. Microwave Symp. Dig., 17–21 June 1996, 3, p. 1289–1292.
-
9)
-
Mielke, J.A., Pope, K.A.: `High-speed fixture interconnects for mixed-signal IC testing', Proc. Int. Test Conf., 10–14 Sept. 1990, p. 891–895.
-
10)
-
Kasukabe, S., Mori, T., Watanabe, T., Shigi, H., Wada, Y., Ariga, A.: `Membrane probe with pyramidal tips for a bare chip testing', Proc. 7th Int. Conf. on Multichip Modules and High Density Packaging, 15–17 April 1998, p. 383–387.
-
11)
-
A.E. Ruehli ,
H. Heeb
.
Circuit models for three-dimensional geometries including dielectrics.
IEEE Trans. Microw. Theory Tech.
,
1507 -
1516
-
12)
-
A. Barber ,
L. Keunmyung ,
H. Obermaier
.
A bare-chip probe for high I/O, high speed testing.
IEEE Trans. Compon. Packag. Manuf. Technol. B, Adv. Packag.
,
4 ,
612 -
619
-
13)
-
Taber, F.L.: `An introduction to area array probing', Proc. Int. Test Conf., 18–23 Oct. 1998, p. 277–281.
-
14)
-
B. Leslie ,
F. Matta
.
Wafer-level testing with a membrane probe.
IEEE Des. Test Comput.
,
1 ,
10 -
17
-
15)
-
J. Jayabalan ,
B.L. Ooi ,
M.S. Leong ,
M.K. Iyer
.
A scaling technique for PEEC analysis using SPICE.
IEEE Microw. Wirel. Compon. Lett.
,
5 ,
216 -
218
-
16)
-
Thacker, H.D., Bakir, M.S., Keezer, D.C., Martin, K.P, Meindl, J.D.: `Compliant probe substrates for testing high pin-count chip scale packages', Proc. Electronic Components and Technology Conf., May 2002, p. 1188–1193.
-
17)
-
C. Wollenberg ,
A. Gurisch
.
Analysis of 3-D interconnect structures with PEEC using SPICE.
IEEE Trans. Electromagn. Compat.
,
4 ,
412 -
417
-
18)
-
R.F. Harrington
.
(1968)
Field computation by moment methods.
-
19)
-
Leung, J., Zargari, M., Wooley, B.A., Wong, S.S.: `Active substrate membrane probe card', Int. Electron Devices Meeting, 10–13 Dec. 1995, p. 709–712.
-
20)
-
A. Sihvola ,
P.J.B. Clarricoats ,
E.V. Jull
.
(1999)
Electromagnetic mixing formulas and applications.
-
21)
-
Keezer, D.C., Zhou, Q., Bair, C., Kuan, J., Poole, B.: `Terabit-per-second automated digital testing', Proc. IEEE Int. Test Conf., 30 Oct. 1 Nov. 2001, p. 1143–1151.
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