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Threshold shift of NMOS transistors due to high energy arsenic source/drain implantation

Threshold shift of NMOS transistors due to high energy arsenic source/drain implantation

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NMOS transistors using high-energy source/drain implantation have been found to have negative threshold shifts. These shifts are shown to be due to arsenic penetration of the polysilicon gate. An implant model of the three-layer structure has been used to predict the threshold shift, and good agreement is found with experimental results.

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