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Optimised travelling-wave amplifier with two parallel-gate transmission lines

Optimised travelling-wave amplifier with two parallel-gate transmission lines

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IEE Proceedings I (Solid-State and Electron Devices) — Recommend this title to your library

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A simple optimisation procedure for the design of travelling-wave amplifiers with two parallel gatelines and a common drain line is presented which utilises the full impedance matching potential involved. The parameters to be optimised for best broad-band performance of the amplifier are the characteristic impedances and, simultaneously, the line section lengths. The predicted performance of a design parallel distributed amplifier, employing eight typical 0.7 μm × 300 μm FETs, i.e. four for each of the two parallel gate-lines, shows 8.8 ± 0.5 dB gain over the frequency range 2–16.5 GHz.

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