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Experimental 1 Mbit DRAM using power reduction techniques

Experimental 1 Mbit DRAM using power reduction techniques

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IEE Proceedings I (Solid-State and Electron Devices) — Recommend this title to your library

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© The Institution of Electrical Engineers
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One of the serious problems which must be overcome in realising a 1 Mbit DRAM is high-power dissipation associated with data-line charging and discharging. To solve this problem, this paper proposes the following three techniques, which permit power reduction by about one-quarter: a multidivided data-line structure, 512 refresh cycles and an on-chip voltage limiter circuit. These techniques are proven to be useful through the design and evaluation of an experimental n-MOS 1 Mbit DRAM with a 46 mm2 chip size. The chip fabricated provides a 295 mW operating power at a 260 ns cycle time despite the fast access time of 90 ns. The possibility of further power reduction is also described.

Inspec keywords: field effect integrated circuits; random-access storage; integrated memory circuits

Other keywords: data-line charging; multidivided data-line structure; power dissipation; NMOS technology; refresh cycles; power reduction techniques; onchip voltage limiter circuit; operating power 295 mW; 1 Mbit DRAM; cycle time 260 ns; access time 90 ns

Subjects: Semiconductor storage; Memory circuits; Other MOS integrated circuits

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