High-density one-device dynamic MOS memory cells
High-density one-device dynamic MOS memory cells
- Author(s): B.S. Kiyoo Itoh and B.S. Hideo Sunami
- DOI: 10.1049/ip-i-1.1983.0024
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- Author(s): B.S. Kiyoo Itoh 1 and B.S. Hideo Sunami 1
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View affiliations
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Affiliations:
1: Central Research Laboratory, Hitachi Ltd., Kitatama, Japan
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Affiliations:
1: Central Research Laboratory, Hitachi Ltd., Kitatama, Japan
- Source:
Volume 130, Issue 3,
June 1983,
p.
127 – 135
DOI: 10.1049/ip-i-1.1983.0024 , Print ISSN 0143-7100, Online ISSN 2053-7980
Performance of one-device cells for dynamic random-access memories is described in terms of signal, noise, speed, soft error and process complexity. From an examination of areal layout and cross-section, five kinds of cells used in commercially available 64 Kbit DRAMs are compared, placing stress on the concept of the folded-data and open-data lines. Somes new DRAM cell concepts, such as a vertically structured capacitor, are proposed on the basis of the paper. The future application limit of the one-device cell seems to exist in the optical lithography of the next generation DRAM of 1 Mbit and beyond, not in the device concept itself.
Inspec keywords: integrated circuit technology; integrated memory circuits; random-access storage; field effect integrated circuits
Other keywords:
Subjects: Lithography (semiconductor technology); Other MOS integrated circuits; Semiconductor storage; Memory circuits
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