© The Institution of Electrical Engineers
Performance of one-device cells for dynamic random-access memories is described in terms of signal, noise, speed, soft error and process complexity. From an examination of areal layout and cross-section, five kinds of cells used in commercially available 64 Kbit DRAMs are compared, placing stress on the concept of the folded-data and open-data lines. Somes new DRAM cell concepts, such as a vertically structured capacitor, are proposed on the basis of the paper. The future application limit of the one-device cell seems to exist in the optical lithography of the next generation DRAM of 1 Mbit and beyond, not in the device concept itself.
References
-
-
1)
-
Itoh, K., Sunami, H.: 1981 symposium on VLSI technology, Dig.Tech.Papers, September 1981, Hawaii, p. 48–49.
-
2)
-
Itoh, K., Hori, R., Masuda, H., Kamigaki, H., Kawamoto, H., Katto, H.: `A single 5 V 64 K dynamic RAM', IEEE Int. Solid-State Circuits Conf. Tech. Dig., February 1980, p. 228–229.
-
3)
-
Sakamoto, M., Kudoh, O., Yamamoto, H., Sekido, K.: `Self-aligned-contact technology for high density MOS VLSI', 1982 symposium on VLSI technology, Dig. Tech. Papers, Oiso, Dept., 1982, Oiso , p. 34–37.
-
4)
-
Yamada, M., Taniguchi, M., Yoshihara, T., takano, S., Matsumoto, H., Nishimura, T., Nakano, T., Gamou, Y.: `Soft error improvement of dynamic RAM with Hi-C structure', IEEE Electron Devices Meet. Tech. Dig., 1980, p. 578–581.
-
5)
-
Sunami, H., Kure, T., Hashimoto, N., Itoh, K., Toyabe, T., Asai, S.: `A corrugated capacitor cell (ccc) for megabit MOS memories', IEEE Int. Electron Devices Meet. Tech. Dig, December 1982, p. 806–808.
-
6)
-
Dennard, R.H.: `Field-effect transistor memor', US Patent 3 387 286, 4 June 1968.
-
7)
-
T.C. May ,
M.H. Woods
.
Alpha-particle-induced soft errors in dynamic memories.
IEEE Trans.
,
2 -
9
-
8)
-
Shimohigashi, K., Masuda, H., Kamigaki, Y., Itoh, K., Hashimoto, N., Arai, E.: `An n-well CMOS dynamic ram', IEEE Electron Devices Meet. Tech. Dig., December 1980, p. 835–836.
-
9)
-
Satoh, S., Denda, M., Takano, S., Fukumoto, T., Tsubouchi, N.: `Soft error improvement in MOS RAMS by the use of epitaxial substrate', Proceedings of the 12th conference on solid-state devices, August 1980, Tokyo, p. 143–147.
-
10)
-
Ahlquist, C.N., Breivogel, J.R., Koo, J.T., McCollum, J.L., Oldham, W.G., Renninger, A.L.: `A 16 K dynamic RAM', IEEE Int Solid State Circuit Conf Tech Dig., February 1980, p. 128–129.
-
11)
-
J.J. Barnes ,
J.M. Deblasi ,
B.E. Deal
.
Low temperature differential oxidation for double polysilicon VLSI devices.
J. Electrochem. Soc.
,
1779 -
1785
-
12)
-
Fujishima, K., Shimotori, K., Ozaki, H., Nakano, T.: `A storage-node-boosted ram with word line delay compensation', IEEE Int. Solid-State Circuits Conf. Tech. Dig., February 1982, p. 66–67.
-
13)
-
Itoh, K.: `Semiconductor memory', US Patent 4 044 340, 23 August 1977.
-
14)
-
V.L. Rideout
.
One-device cells for dynamic random-access memories: a tutorial.
IEEE Trans.
,
839 -
852
-
15)
-
White, L.S., Hong, J.N.H., Redwine, D.J., Mohan Rao, G.R.: `A 5 V-Only 64 k dynamic RAM', IEEE Int. Solid-State Circuits Conf. Tech. Dig., February 1980, p. 230–231.
-
16)
-
Ohta, K., Yamada, K., Saitoh, M., Shiraki, H., Nakamura, A., Shimizu, K., Tarui, Y.: `A stacked high capacitor RAM', IEEE Int. Solid-State Circuit Conf. Tech. Dig., February 1980, p. 66–67.
-
17)
-
H. Masuda ,
R. Hori ,
Y. Kamigaki ,
K. Itoh
.
Single 5V, 64K RAM with scaled-down mos structure.
IEEE Trans.
,
1607 -
1612
-
18)
-
H. Sunami ,
M. Koyanagi ,
N. Hashimoto
.
Intermediate oxide formation in double-polysilicon gate MOS structure.
J. Electrochem. Soc.
,
2499 -
2506
-
19)
-
P.K. Chatterjee ,
G.W. Taylor ,
R.L. Easley ,
H.-S. fu ,
A.F. Tasch
.
A survey of high-density dynamic ram cell concepts.
IEEE Trans.
,
827 -
839
-
20)
-
Taniguchi, M., Ohbayashi, Y., Yamada, M., Nagasawa, Y., Sato, S., Nakano, T.: `High performance dynamic RAM using double aluminum layer', 1982 symposium on VLSI technology, dig. tech. papers, September 1982, Osio , p. 62–63.
-
21)
-
Mitsusada, K., Katto, H., Toyabe, T.: `Design for alpha immunity of MOS dynamic RAMs', IEEE Int. Electron Devices Meet. Tech. Dig., 1981, p. 36–39.
-
22)
-
H.H. Chao ,
R.H. Dennard ,
M.Y. Tsai ,
M.R. Wordeman ,
A. Cramer
.
A 34μm2 dram cell fabriated with a 1μm single-level polycide fet technology.
IEEE J. Solid-State Circuits
,
499 -
505
-
23)
-
Morie, T., Minesgishi, K., Kimizuka, M., Nakajima, S.: `An application of deep moat to capacitor', Japan Society of Applied Physics, 28–30 September 1982, Fall Meeting (Domestic), Abstracts 30p-Q-6.
-
24)
-
H. Masuda ,
H. Hori ,
Y. Kamigaki ,
K. Itoh ,
H. Kawamoto ,
H. Katto
.
Single 5V-only 64K RAM with scaled-down mos structure.
IEEE Trans.
,
1607 -
1612
-
25)
-
Ishihara, M., Matsumoto, T., Shimizu, S., Mitsusada, K., Shimohigashi, K., Mano, T.: `A 256 K dynamic MOS RAM with alpha immunity and redundancy', IEEE Int. Solid-State Circuits Conf. Tech. Dig, February 1982, p. 74–75.
-
26)
-
Dennard, R.H., Sai-halasz, G.A.: `Modeling and control of alpha-particle effects in scaled-down vlsi circuits', 1981 symposium on VLSI technology, tech. dig. papers, September 1981, Hawaii, p. 44–45.
-
27)
-
S. Ogura ,
P.J. Tsang ,
W.W. Walker ,
D.L. Critchlow
.
Design and charateristics of the lightly doped drain-source(LDD) insulated gate field-effect transistor.
IEEE Trans.
,
1359 -
1367
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