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High-density one-device dynamic MOS memory cells

High-density one-device dynamic MOS memory cells

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Performance of one-device cells for dynamic random-access memories is described in terms of signal, noise, speed, soft error and process complexity. From an examination of areal layout and cross-section, five kinds of cells used in commercially available 64 Kbit DRAMs are compared, placing stress on the concept of the folded-data and open-data lines. Somes new DRAM cell concepts, such as a vertically structured capacitor, are proposed on the basis of the paper. The future application limit of the one-device cell seems to exist in the optical lithography of the next generation DRAM of 1 Mbit and beyond, not in the device concept itself.

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