Amin, A.A.M.: 'Speed optimised array architecture for flash EEPROMs', IEE Proceedings G (Circuits, Devices and Systems), 1993, 140, (3), p. 177-181, DOI: 10.1049/ip-g-2.1993.0028 IET Digital Library, https://digital-library.theiet.org/;jsessionid=2vpnu3lok844j.x-iet-live-01content/journals/10.1049/ip-g-2.1993.0028