http://iet.metastore.ingenta.com
1887

Speed optimised array architecture for flash EEPROMs

Speed optimised array architecture for flash EEPROMs

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IEE Proceedings G (Circuits, Devices and Systems) — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The paper describes a new architecture for a split-gate flash EEPROM memory array. The new array architecture provides increased speed and less susceptibility to soft writes during read operations. A unique circuit design and operation method obviates the need for applying high erase voltage in the path between the memory array and the sense amplifier. This allows all the transistors in this speed path to be fabricated as low voltage minimum channel length devices, thereby increasing their speed of operation and consequently the speed of the memory device as a whole. The new architecture, however, requires the addition of two extra rows of nonmemory cell transistors in addition to following a strict programming sequence to guard against spurious programming of unselected cells.

References

    1. 1)
      • McConnell . An experimental 4-Mb flash EEPROM with sector erase. IEEE JSSC , 484 - 491
    2. 2)
      • V. Kynett . A 90-ns one million erase/program cycle 1-Mbit flash memory. IEEE JSSC , 1259 - 1264
    3. 3)
      • Kume, H.: `A flash erase EEPROM cell with an asymmetric source and drain structure', IEDM Tech. Digest, 1987, p. 560–563.
    4. 4)
      • F. Masuoka . A 256-kbit flash E2PROM using triple polysilicon technology. IEEE JSSC , 4 , 548 - 552
    5. 5)
      • Gill, M.: `A 5-Volt only contactless array 256 kbit flash EEPROM technology', IEDM Tech. Digest, 1988, p. 428–431.
    6. 6)
      • Mukherjee, S.: `A single transistor EEPROM cell and its implementation in a 512k CMOS EEPROM', IEDM Tech. Digest, 1985, p. 616–619.
    7. 7)
      • Cernea, R.: `A 1 Mb flash EEPROM', IEEE ISSCC Tech. Digest, 1989, p. 138–139.
    8. 8)
      • Samachisa, G.: `A 128 K flash EEPROM using double polysilicon technology', ISSCC Digest, 1987, p. 76–77.
    9. 9)
      • S.B. Ali . A 50-ns 256 k CMOS split-gate EPROM. IEEE JSSC , 79 - 84
    10. 10)
      • A. Amin . Design, selection and implementation of flash erase EEPROM memory cells. IEE Proc. G , 2 , 370 - 376
    11. 11)
      • F. Conti , M. Conti . Surface breakdown in silicon planar diodes equipped with field plate. Solid State Electron. , 93 - 105
    12. 12)
      • Amin, A.: `Novel architecture for a flash erase EPROM memory', Application 4 999 812 1991, , US Patent.
    13. 13)
      • K. Prall . Characterization and suppression of drain coupling in submicrometer EPROM cells. IEEE Trans. , 2463 - 2468
    14. 14)
      • Verma, G., Mielke, N.: `Reliability performance of ETOX based flash memories', Proceedings 1988 IEEE Reliability Physics Symposium, p. 158–166.
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-g-2.1993.0028
Loading

Related content

content/journals/10.1049/ip-g-2.1993.0028
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address