SEESIM: a fast synchronous sequential circuit fault simulator with single-event equivalence

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SEESIM: a fast synchronous sequential circuit fault simulator with single-event equivalence

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The paper presents a concept of single event equivalence to be used in the sequential circuit fault simulator. The concept dynamically identifies the equivalent faults for a simulated pattern. It combines advantages of the fanout-free region, critical path tracing and the dominator concept, which were applicable only to combinational circuit fault simulation. The implemented fault simulator, SEESIM, based on the concept, demonstrated a performance superior to that of a state-of-the-art concurrent fault simulator, and comparable to that of parallel-pattern single-fault propagation simulators. It requires a minimal amount of memory and, because of its simplicity, can be easily extended to multilogic or higher level simulation.

Inspec keywords: many-valued logics; fault location; logic testing; sequential circuits

Other keywords: SEESIM; fault simulator; dominator concept; synchronous sequential circuit; simulated pattern; multilogic; critical path tracing; single-event equivalence; fanout-free region

Subjects: Electronic engineering computing; Logic and switching circuits; Computerised instrumentation; Computer-aided logic design; Logic circuits

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