http://iet.metastore.ingenta.com
1887

Associative memory integrated circuit based on neural mutual inhibition

Associative memory integrated circuit based on neural mutual inhibition

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IEE Proceedings G (Circuits, Devices and Systems) — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Hardware associative or content-addressable memory (CAM) which finds in one operation the nearest match to input data among several templates is very crucial in the design of effective pattern recognition systems. We call this type of memory a relaxative CAM (RCAM) as opposed to the traditional exact-match CAM design. A compact implementation of an RCAM calls for the employment of a neural network model. In the paper we present the design and silicon implementation of an RCAM using a neural mutual inhibition network as the relaxation circuit. Spice simulations of the mutual inhibition and the RCAM performance are presented. A 16-word 12-bit IC has been fabricated through MOSIS using 2 μm double-metal CMOS technology. The RCAM chip was tested and its correct functionality has been fully verified.

References

    1. 1)
      • Slade, A.E., McMahon, H.O.: `A cryotron catalog memory system', Proceedings of the Eastern Joint Computer Conference, December 1956, 10, p. 115–120.
    2. 2)
      • A.G. Hanlon . Content-addressable and associative memory systems: a survey. IEEE Trans. , 4 , 509 - 521
    3. 3)
      • B. Parhami . Associative memories and processors: an overview and selected bibliography. Proc. IEEE , 722 - 730
    4. 4)
      • T. Kohonen . (1980) , Content-addressable memories.
    5. 5)
      • L. Chisvin , R.J. Duckworth . Content-addressable and associative memory: alternatives to the ubiquitous RAM. IEEE Comput. Mag. , 7 , 51 - 64
    6. 6)
      • K. Nakano . Association — a model of associative memory. IEEE Trans. Syst. Man. Cybern. , 380 - 388
    7. 7)
      • Johnson, L.G.: `Neural network associative memories', Proceedings of the IEEE 31st Midwest Symposium on Circuits and Systems, August 1988, p. 161–164.
    8. 8)
      • Graf, H.P., DeVegvar, P.: `A CMOS implementation of a neural network model', Proceedings of the Stanford Conference on Advance Research, 1987, p. 351–367, VLSI.
    9. 9)
      • H.P. Graf , L.D. Jackel , W.E. Hubbard . VLSI implementation of a neural network model. IEEE Comput. Mag. , 3 , 41 - 49
    10. 10)
      • R.P. Lippmann . An introduction to computing with neural nets. IEEE ASSP Mag. , 2 , 4 - 22
    11. 11)
      • T.J. Chaney , C.E. Molnar . Anomalous behavior of synchronizer and arbitercircuits. IEEE Trans. , 4 , 421 - 422
    12. 12)
      • O. Minato , T. Masuhara , T. Sasaki , H. Nakamura , Y. Sakai , T. Yasui , K. Uchibori . 2K × 8 Bit Hi-CMOS static RAMS. IEEE J. Solid-State Circuits , 656 - 660
    13. 13)
      • L.G. Johnson , S.M.S. Jalaleddine . Parameter variations in MOS CAM with a mutual inhibition network. IEEE Trans. Circuits Syst. , 9 , 1021 - 1029
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-g-2.1992.0071
Loading

Related content

content/journals/10.1049/ip-g-2.1992.0071
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address