References

• 1. 1)
     • L. Snyder . Introduction to the configurable, highly parallel computer. IEEE Comput. Mag. , 47 - 56
  2. 2)
     • Karabernou, S.M., Mazaré, G., Payan, E., Rubini, P.: `A network with small general processing units for fine grain parallelism', Proc. Int. Workshop Algorithms and Parallel VLSI Architectures, June 1990, France, Pont-à-Mousson, p. 197–200.
  3. 3)
     • H.T. Kung , C.E. Leiserson , C. Mead , L. Conway . (1980) Algorithms for VLSI processor arrays, Introduction to VLSI systems.
  4. 4)
     • I. Koren , B. Mendelson , I. Peled , G.M. Silberman . A data-driven VLSI array for arbitrary algorithms. IEEE Comput. Mag. , 30 - 43
  5. 5)
     • NCR, Drayton, `Geometric arithmetic parallel processor manual', 1984, NCR.
  6. 6)
     • C.R. Ward , E.B. Davie , W. Moore , A. McCabe , R. Urquhart . (1986) The application and development of wavefront array processors for advanced front-end signal processing systems, IEEE Systolic Arrays.
  7. 7)
     • A.L. Fisher , H.T. Kung , L.M. Monier , Y. Dohi . Architecture of the PSC: A programmable systolic chip. IEEE Comp. Arch. , 48 - 53
  8. 8)
     • S.Y. Kung . (1988) , VLSI array processors.
  9. 9)
     • R. Freeman . User-programmable gate arrays. IEEE Spectrum Mag. , 13 , 32 - 35
  10. 10)
      • Vasell, J., Vasell, J.: `A wavefront array for functional program execution', 65, Technical Report, April 1990.
  11. 11)
      • H.T. Kung . Why systolic architectures?. IEEE Computer , 37 - 46
  12. 12)
      • J.V. McCanny , J.G. McWhirter . Some systolic array developments in the United Kingdom. IEEE Comput. Mag. , 51 - 63
  13. 13)
      • P.M. Kogge . (1981) , Architecture of pipelined computers.
  14. 14)
      • A. Corry , K. Patel . Architecture of a CMOS correlator. IEEE Comput. Mag. , 522 - 525
  15. 15)
      • L.W. Tucker , G.G. Robertson . Architecture and applications of the connection machine. IEEE Comput. Mag. , 8 , 26 - 38
  16. 16)
      • P. Bertin , D. Roncin , J. Vuillemin , J. McCanny , J. McWhirter , E. Swartzlander . (1989) Introduction to active memories, Systolic array processors.
  17. 17)
      • R.C. Minnick . A survey of microcellular research. J. ACM , 2 , 203 - 241
  18. 18)
      • Oldfield, D.E., Reddaway, S.F.: `An image understanding performance study on the ICL distributed array processor', IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, 1985, p. 256–264.
  19. 19)
      • T. Kean , J. Gray , J. McCanny , J. McWhirter , E. Swartzlander . (1989) Configurable hardware: two case studies of micro-grain computation, Systolic array processors.
  20. 20)
      • A.W. Burks . (1970) , Essays on cellular automata.
  21. 21)
      • T.J. Fountain . Clip4 parallel processing system. IEE Proc. E , 5 , 219 - 224
  22. 22)
      • Batcher, K.E.: `Architecture of the MPP', IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, 1983, p. 170–174.
  23. 23)
      • Inmos Ltd., Bristol, UK, `Reference manual transputer architecture', July 1987, p. 1–25, INMOS.
  24. 24)
      • (1986) , The programmable gate array design handbook.
  25. 25)
      • R.C. Minnick . Cutpoint celluar logic. IEEE Trans. , 685 - 698
  26. 26)
      • Borkar, S., Cohn, R., Cox, G., Gleason, S., Gross, T., Kung, H.T., Lam, M., Moore, B., Peterson, C., Pieper, J., Rankin, L., Tseng, P.S., Sutton, J., Urbanski, J., Webb, J.: `iWARP: An integrated solution to high-speed parallel computing', Proc. IEEE Supercomputing Conf., November 1988, p. 330–339.
  27. 27)
      • S.Y. Kung , S.-C. Lo , S.N. Jean , J.N. Hwang . Wave-front array processors — concept to implementation. IEEE Comput. Mag. , 18 - 33
  28. 28)
      • E-Beam Logic Series, Texas Instruments, UK, `TAAC gate arrays users manual', 1988, TEXAS INSTRUMENTS.