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1887

8 × 8 bit pipelined dadda multiplier in CMOS

8 × 8 bit pipelined dadda multiplier in CMOS

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Parallel multiplication schemes for VLSI have traditionally been chosen for their regular layout. Unfortunately, this has meant using algorithms which are not time-optimal. In the paper, we present an 8 × 8 bit time-optimal multiplier using the Dadda scheme implemented as a 7-stage linear pipeline. The design uses automated layout techniques to avoid the problems associated with the irregularity of the scheme, and a 3 μm n-well CMOS process with two layers of metal. The use of multiple levels of metal reduces the delay associated with the interconnection between cells and also permits the over-routing of active circuitry. A new pipelined carry look-ahead adder is used for the final summation, and this provides a significant contribution to the performance of the multiplier. A set of cells was designed for the multiplier and some aspects of their design are discussed. In particular, a previously unreported Vdd overshoot problem in an existing exclusive-OR gate circuit is described and explained. The multiplier is expected to operate at a maximum clock frequency of at least 50 MHz.

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