Testing of random access memories: theory and practice

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Testing of random access memories: theory and practice

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© The Institution of Electrical Engineers
Published

Testing of random access memories (RAMs) gives more and more problems. The dimensions are growing rapidly and the denser devices result in more complex failure modes. The goal of our research was the evaluation of the existing test patterns in SRAM testing. A large diversity of test patterns was executed on silicon SRAM wafers and results were compared. The results affirm the conclusions: that the use of a well-defined fault model results into a more efficient test for permanent faults; and that the twocoupling fault model appears to be very efficient.

Inspec keywords: integrated memory circuits; random-access storage; integrated circuit testing; fault location

Other keywords: RAMs; two-coupling fault model; SRAM testing; test patterns; random access memories; Si

Subjects: Semiconductor storage; Memory circuits

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