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Five-level inverter scheme for an induction motor drive with simultaneous elimination of common-mode voltage and DC-link capacitor voltage imbalance

Five-level inverter scheme for an induction motor drive with simultaneous elimination of common-mode voltage and DC-link capacitor voltage imbalance

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The simultaneous elimination of common-mode voltage and DC-link capacitor voltage imbalance is achieved in a five-level inverter scheme for an induction motor drive throughout its operating range. A dual five-level inverter-fed open-end-winding induction motor structure is used for the proposed drive. Initially, the operating limitations of achieving this dual task for the five-level inverter configuration are investigated for a single DC power supply. Subsequently, a switching strategy for a five-level inverter topology with two DC power supplies is proposed to achieve the dual task over the entire speed range of the drive. The proposed drive offers a simple power-bus structure with more redundant switching combinations for inverter voltage vectors, and requires a lower voltage-blocking capacity of the power devices as compared with the conventional single five-level inverter-fed drive. As only the availability of redundant switching combinations for inverter voltage vectors is exploited, the dual task is achieved without disturbing the fundamental component of the inverter output voltage and the scheme does not need any extra control circuit hardware. Experimental verification of the proposed scheme is done on a 1.5 kW induction motor drive in the linear as well as overmodulation range.

References

    1. 1)
      • Choi, N.S., Cho, J.G., Cho, G.H.: `A general circuit topology of multilevel inverter', Proc. of 22nd Annual IEEE Conf., PESC‘91, 24–27 June 1991, p. 96–103.
    2. 2)
      • M.R. Baiju , K.K. Mohapatra , R.S. Kanchan , K. Gopakumar . A dual two-level inverter scheme with common mode voltage elimination for an induction motor drive. IEEE Trans. Power Electron. , 3 , 794 - 805
    3. 3)
      • A.V. Jouanne , S. Dai , H. Zhang . A multilevel inverter approach providing DC-link balancing, ride-through enhancement, and common-mode voltage elimination. IEEE Trans. Ind. Electron. , 4 , 739 - 745
    4. 4)
      • Tekwani, P.N., Kanchan, R.S., Gopakumar, K., Vezzini, A.: `A five-level inverter topology with common-mode voltage elimination for induction motor drives', Accepted for 11th EPE Conf., 11–14 September 2005, Dresden, Germany.
    5. 5)
      • Kanchan, R.S., Tekwani, P.N., Gopakumar, K.: `Three-level inverter scheme with common-mode voltage elimination and DC-link capacitor-voltage balancing for an open-end-winding induction motor drive', Proc. of IEEE Int. Conf. on. Electric Machines and Drives, IEMDC-2005, 15–18 May 2005, San Antonio, USA, p. 1445–1452.
    6. 6)
      • R.S. Kanchan , P.N. Tekwani , M.R. Baiju , K. Gopakumar , A. Pittet . Three-level inverter configuration with common-mode elimination for induction motor drive. IEE Proc. EPA , 2 , 261 - 270
    7. 7)
      • F.Z. Peng . A generalized multilevel inverter topology with self voltage balancing. IEEE Trans. Ind. Appl. , 2 , 611 - 618
    8. 8)
      • M. Marchesoni , P. Tenca . Diode-clamped multilevel converters: a practicable way to balance DC-link voltages. IEEE Trans. Ind. Electron. , 4 , 752 - 765
    9. 9)
      • Newton, C., Sumner, M.: `Neutral-point control for multilevel inverters: theory, design and operational limitations', Proc. of IEEE IAS Conf., 5–9 Oct. 1997, New Orleans, p. 1336–1343.
    10. 10)
      • C. Newton , M. Summer . Novel technique for maintaining balanced internal DC-link voltages in diode-clamped five-level inverters. IEE Proc. EPA , 3 , 341 - 349
    11. 11)
      • H. Zhang , A. Jouanne , S. Dai . Multilevel inverter modulation schemes to eliminate common-mode voltages. IEEE Trans. Ind. Appl. , 6 , 1645 - 1653
    12. 12)
      • P.C. Loh , D.G. Holmes , Y. Fukuta , T.A. Lipo . Reduced common-mode modulation strategies for cascaded multilevel inverters. IEEE Trans. Ind. Appl. , 5 , 1386 - 1395
    13. 13)
      • J. Pou , R. Pindado , D. Boroyevich . Voltage-balance limits in four-level diode-clamped converters with passive front ends. IEEE Trans. Ind. Electron. , 1 , 190 - 196
    14. 14)
      • H.J. Kim , H.D. Lee , S. Sul . A new PWM strategy for common-mode voltage reduction in neutral-point-clamped inverter-fed AC motor drives. IEEE Trans. Ind. Appl. , 6 , 1840 - 1845
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