© The Institution of Electrical Engineers
In this paper, a new approach to repairability/unrepairability detection for VLSI memory chips with redundancy is presented. An heuristic, yet efficient approach, is proposed. New conditions for detection are presented and fully analysed. These are based on a more accurate estimation of the regions of repairability and unrepairability. The main benefit of this approach is its practicality with respect to fast execution time and the improved ability to diagnose a VLSI redundant memory before the generation of the repair-solution. A new repair algorithm which utilizes a ternary tree approach is also presented.
References
-
-
1)
-
R.P. Cenker
.
A fault tolerant 64k dynamic random access memory.
IEEE Trans.
,
6 ,
853 -
860
-
2)
-
C.-L. Wey ,
F. Lombardi
.
On the repair of redundant RAMs.
IEEE Trans. on CAD
,
2 ,
222 -
231
-
3)
-
J.R. Day
.
A fault-driven comprehensive redundancy algorithm for repair of dynamic RAMs.
IEEE Design and Test of Computers
,
3 ,
33 -
44
-
4)
-
Kuo, S.-Y., Fuchs, W.K.: `Efficient spare allocation in reconfigurable arrays', Proc. ACM/IEEE DAC, 1986, p. 385–390.
-
5)
-
R.C. Evans
.
Testing repairable RAMs and mostly good memories.
Proc. IEEE ITC
,
49 -
55
-
6)
-
Huang, W.K., Lombardi, F.: `Approaches for the repair of VLSI/WSI RRAMs by row/column deletion', Proc. Fault Tolerant Computing Symposium, June 1988, , p. 342–347.
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-e.1990.0013
Related content
content/journals/10.1049/ip-e.1990.0013
pub_keyword,iet_inspecKeyword,pub_concept
6
6