Repairability/unrepairability detection technique for yield enhancement of VLSI memories with redundancy

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Repairability/unrepairability detection technique for yield enhancement of VLSI memories with redundancy

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© The Institution of Electrical Engineers
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In this paper, a new approach to repairability/unrepairability detection for VLSI memory chips with redundancy is presented. An heuristic, yet efficient approach, is proposed. New conditions for detection are presented and fully analysed. These are based on a more accurate estimation of the regions of repairability and unrepairability. The main benefit of this approach is its practicality with respect to fast execution time and the improved ability to diagnose a VLSI redundant memory before the generation of the repair-solution. A new repair algorithm which utilizes a ternary tree approach is also presented.

Inspec keywords: trees (mathematics); redundancy; integrated circuit testing; integrated memory circuits; VLSI

Other keywords: yield enhancement; redundancy; unrepairability; VLSI memories; ternary tree; repairability

Subjects: Semiconductor storage; Memory circuits

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