Content-addressable memories applied to execution of logic programs

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Content-addressable memories applied to execution of logic programs

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© The Institution of Electrical Engineers
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The paper describes a number of techniques for using content-addressable memory to speed up the execution of logic programs for both single and multiple processor implementations. The techniques shown allow for significant speed-ups in unification, clause selection, branch switching, variable handling and garbage collection. For multiple processor implementations, the literal ordering and environment join algorithms are also improved. In addition to the speed improvements, some simplification of software results from performing indexing operations in content-addressable memory.

Inspec keywords: logic programming; content-addressable storage; multiprocessing systems

Other keywords: variable handling; literal ordering; multiple processor; unification; execution of logic programs; branch switching; garbage collection; clause selection; indexing operations; environment join algorithms

Subjects: Artificial intelligence (theory); Systems analysis and programming; Other digital storage

References

    1. 1)
      • Ogura, T., Yamada, S-I., Yamada, J.: `A 20 Kb CMOS Associative Memory LSI for Artificial Intelligence Machines', Proceedings of the 1986 IEEE International Conference on Computer Design: VLSI in Computers, October 1986, , p. 547–577.
    2. 2)
      • Hausman, B., Ciepielewski, A., Haridi, S.: `OR-parallel Made Efficient on Shared Memory Multiprocessors', Proceedings of the 1987 International Symposium on Logic Programming, September 1987, , p. 69–78.
    3. 3)
      • R.M. Colomb . A Clause Indexing System for Prolog Based on Superimposed Coding. Austr. Comput. J. , 1
    4. 4)
      • Warren, D.H.D.: `Efficient Prolog Memory Management for Flexible Control Strategies', Proceedings of the 1984 International Symposium on Logic Programming, February 1984, , p. 198–202.
    5. 5)
      • Tick, E., Warren, D.H.D.: `Towards a Pipeline Prolog Processor', Proceedings of the 1984 International Symposium on Logic Programming, February 1984, , p. 198–202.
    6. 6)
      • Warren, D.H.D.: `An Abstract Prolog Instruction Set', 309, SRI Technical Note, October 1983.
    7. 7)
      • Warren, D.H.D.: `The SRI Model for OR-Parallel Execution of Prolog-Abstract Design and implementation issues', Proceedings of the 1987 International Symposium on Logic Programming, September 1987, , p. 92–102.
    8. 8)
      • P.M. Kogge , J.V. Oldfield , M.R. Brule , C.D. Stormon , Delgado-Frias Moore . (1989) VLSI and Rule-Based Systems, VLSI for Artificial Intelligence.
    9. 9)
      • Oldfield, J.V., Stormon, C.D., Brule, M.R.: `The Application of VLSI Content-Addressable Memory to the Acceleration of Logic Programming Systems', Proceedings CompEuro, 1987, p. 27–30.
    10. 10)
      • DeGroot, D.: `Restricted AND-Parallelism', Proceedings of the International Conference on Fifth Generation Computer Systems, November 1984, , p. 471–478.
    11. 11)
      • Stormon, C.D., Brule, M.R., Oldfield, J.V., Ribeiro, J.C.D.F.: `An Architecture Based on Content-Addressable Memory for the Rapid Execution of Prolog', Proceedings of the Fifth International Conference on Logic Programming, August 1988, , p. 1448–1473.
    12. 12)
      • C.G. Sodini , J.P. Wade . Dynamic Cross-coupled Bitline Content Addressable Memory Cell for High Density Arrays. IEEE J. Solid-State Circ. , 119 - 121
    13. 13)
      • J.A. Robinson . A Machine-oriented Logic Based on the Resolution Principle. J. ACM , 1 , 23 - 41
    14. 14)
      • Brule, M.R.: `The Use of Content-Addressable Memory in Executing Logic Programs', 8813, CASE Center Technical Report, October 1988.
    15. 15)
      • Ribeiro, J.C.D.F.: `CAMAndOr: An Implementation of Logic Programming Exploiting Coarse and Fine Grain Parallelism', 8815, CASE Center Technical Report, October 1988.
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