Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture

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Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture

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© The Institution of Electrical Engineers
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The paper reports an investigation into the design constraints, trade-offs and implementation issues involved in the design of a large content-addressable memory (CAM) for a VLSI CMOS high-speed associative chip architecture: the single chip array processing element SCAPE associative parallel processor. It includes results from a study into determining the general electrical and physical characteristics of a range of CAM cells; details from a case study of the SCAPE chip that predicts the performance of CAMs within a VLSI-based parallel processing computer system, together with the overall impact the CAM design has on the SCAPE chip performance; the selection and implementation engineering of the most cost-effective CAM design for the SCAPE chip.

Inspec keywords: VLSI; content-addressable storage; CMOS integrated circuits; parallel processing

Other keywords: VLSI-based parallel processing computer system; content-addressable memory; physical characteristics; design; electrical characteristics; VLSI CMOS chip architecture; single chip array processing element SCAPE associative parallel processor; selection; implementation

Subjects: Memory circuits; Multiprocessing systems; CMOS integrated circuits; Semiconductor storage

References

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      • T. Kohonen . (1980) , Content-addressable Memories.
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      • R.M. Lea . SCAPE: a Single-chip Array Processing Element for Signal and Image Processing. IEE Proc. E, Comput. & Digital Tech. , 145 - 151
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      • S.R. Jones , R.M. Lea , G. Saucier , J. Trilhe . Content-addressable memories for WSI, Wafer-scale Integration.
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      • T. Ogura , S. Yamada , T. Nikaido . A 4 Kb Associative Memory LSI. IEEE J. , 1277 - 1282
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      • Jalowiecki, I.P., Lea, R.M.: `SCAPE — A High Performance Image and Signal Array Processor Chip', Proceedings 3rd Silicon Design Conference, 1986, London, p. 345–354, 31/33 High Holborn.
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