© The Institution of Electrical Engineers
A parallel image processor (PIP) consisting of eight Texas Instruments TMS32010 digital signal processors is described. The architecture is designed for image-processing applications and two common pattern-recognition algorithms, i.e. edge detection followed by thinning are implemented achieving a total processing time of less than one second for a 256 × 256 pixel image. The advantages and limitations of using the TMS32010 as a fast signal processor are described. Problems encountered in programming the parallel processors and ways to overcome them are highlighted.
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Morgan, D.R., Silverman, H.F.: `An investigation into the efficiency of a parallel TMS320 architecture: DFT and speech filterbank applications', Proceedings of ICASSP, 1985, p. 42.1.1–42.1.4.
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