Elimination algorithm: a method for fault diagnosis in combinational circuits based on an effect-cause analysis

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Elimination algorithm: a method for fault diagnosis in combinational circuits based on an effect-cause analysis

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© The Institution of Electrical Engineers
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In the paper we develop an approach to fault diagnosis in combinational circuits yielding a new method based on an effect-cause analysis. In our method the circuit under test N* is studied by using a description of its behaviour called the operation map. Depending on the set of tests applied, this description may allow the fault in N* to be detected before, and independently of, being located. The elimination of inputs in the operation map allows us to find the fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). The method presented does not require a fault dictionary, fault enumeration or knowledge of the values expected in the fault-free circuit, and it makes possible applications such as obtaining faults not detected by a given test (including redundant faults), the identification of faults which cannot be modelled as stuck-at faults and other applications characteristic of this type of analysis.

Inspec keywords: fault location; combinatorial circuits; logic testing

Other keywords: fault-free circuit; elimination algorithm; stuck-at faults; combinational circuits; fault diagnosis; redundant faults; applications characteristic; effect-cause analysis

Subjects: Logic circuits; Logic design methods

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