Fault diagnosis for a multistage Banyan interconnection network

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Fault diagnosis for a multistage Banyan interconnection network

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© The Institution of Electrical Engineers
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Multistage networks play an important role in parallel-processing architectures and particularly in reconfigurable structures, as they provide the ability to switch paths between modules according to both the requirements of throughput and fault occurrence. In this respect, effective fault diagnosis techniques of these devices are highly desirable to cover these switching modes. In the paper diagnostic tests applicable to SW Banyan networks (SWBNs) with a spread of two and a fanout of two are presented.

Inspec keywords: computer networks; parallel processing; fault tolerant computing; computer architecture

Other keywords: modules; fault diagnosis techniques; fault occurrence; multistage Banyan interconnection network; parallel-processing architectures; reconfigurable structures

Subjects: Computer networks and techniques; Multiprocessing systems; Computer architecture; Performance evaluation and testing

References

    1. 1)
      • Lipovski, G.J., Triphati, A.: `A reconfigurable varistructure array processor', Proc. Int. Conf. Paral. Processing, 1977, p. 165–174.
    2. 2)
      • C.L. Wu , T.Y. Feng . Fault diagnosis for a class of multistage interconnection networks. IEEE Trans. , 10 , 743 - 758
    3. 3)
      • C.-L. Wu , T.-Y. Feng . On a class of multistage interconnection networks. IEEE Trans. , 8 , 694 - 702
    4. 4)
      • T. Feng . Data manipulating functions in parallel processors and their implementations. IEEE Trans. , 3 , 309 - 318
    5. 5)
      • V. Cherkasskey , E. Opper , M. Malek . Reliability and fault diagnosis analysis of fault-tolerannt multistage interconnection networks. FTCS , 246 - 253
    6. 6)
      • R.A. Decarlo , R. Saeks . (1981) , Interconnected dynamical systems.
    7. 7)
      • C. Mead , L. Conway , C. Seitz . (1980) , Introduction to VLSI systems.
    8. 8)
      • D.K. Lawrie . Access and alignment of data in an array processor. IEEE Trans. , 12 , 1145 - 1155
    9. 9)
      • S.I. Kartashev , S.P. Kartashev . Dynamic architectures; problems, and solutions. Computer , 7 , 26 - 40
    10. 10)
      • Batcher, K.E.: `The flip network in STARAN', Proc. Int. Conf. Paral. Processing, 1976, p. 65–71.
    11. 11)
      • S.I. Kartashev , S.P. Kartashev . (1982) , Designing and programming modern computers and systems: Vol. I, LSI modular computer systems.
    12. 12)
      • M.C. Pease . The indirect binary n-cube microprocessor array. IEEE Trans. , 5 , 548 - 573
    13. 13)
      • J.P. Gray . (1981) , VLSI 81; very large scale integration.
    14. 14)
      • S.I. Kartashev , S.P. Kartashev , C.V. Ramamoorthy . Adaptation properties for dynamic architectures. AFIPS Conf. Proc , 543 - 556
    15. 15)
      • J.H. Patel . Performance of processor-memory interconnections for multiprocessors. IEE Trans. , 10 , 771 - 780
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