Defect tolerance in multiple-FPGA systems

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Defect tolerance in multiple-FPGA systems

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Published

SRAM-based field programmable gate arrays (FPGAs) have an inherent capacity for defect tolerance. A simple scheme that exploits this potential in multiple-FPGA systems is proposed. The symmetry of the system is exploited to yield a large number of possible mappings of bitstreams on FPGAs, which results in a high probability that at least one functional mapping exists. It is shown that the behaviour of a system built using a large number of defective FPGAs approaches that of the ideal defect-free system. Various interconnection topologies such as the tree, the crossbar and a hybrid form are compared.

Inspec keywords: field programmable gate arrays; fault tolerant computing; SRAM chips

Other keywords: defect tolerance; defective FPGA; field programmable gate array; interconnection topology; SRAM; multiple FPGA system; static random access memory; functional bitstream mapping; defect free system

Subjects: Logic circuits; Performance evaluation and testing; Memory circuits; Semiconductor storage; Logic and switching circuits

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