Your browser does not support JavaScript!

Memory access scheduling and binding considering energy minimisation in multi-bank memory systems: integrated approach

Memory access scheduling and binding considering energy minimisation in multi-bank memory systems: integrated approach

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IEE Proceedings - Computers and Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Memory-related activity is one of the major sources of energy consumption in embedded systems. Many types of memories used in embedded systems allow multiple operating modes (e.g. active, standby, nap, power-down) to facilitate energy saving. Furthermore, it has been known that the potential energy saving increases when the embedded systems use multiple memory banks in which their operating modes are controlled independently. The authors propose a compiler-directed integrated approach to the problem of maximally utilising the operating modes of multiple memory banks by solving the three important tasks simultaneously: (1) assignment of variables to memory banks, (2) scheduling of memory access operations and (3) determination of operating modes of banks. Specifically, for an instance of tasks 1 and 2, the authors formulate task 3 as a shortest path (SP) problem in a network and solved it optimally. Then, an SP-based heuristic that solves tasks 2 and 3 efficiently in an integrated fashion is developed. Then the proposed approach is extended to address the limited register constraint in the processor. From experiments with a set of benchmark programs, it is confirmed that the proposed approach is able to reduce the energy consumption by 15.76% over that by the conventional approach.


    1. 1)
      • Cho, J., Paek, Y., Whalley, D.: `Efficient register and memory assignment for non-orthogonal architecture via graph coloring and MST algorithms', ACM Joint Conf. LCTES-SCOPES, 2002, p. 130–138.
    2. 2)
      • De La Luz, V., Sivasubramaniam, A., Kandemir, M., Vijaykrishnan, N., Irwin, M.J.: `Scheduler-based DRAM energy management', Proc. DAC, 2002, p. 697–702.
    3. 3)
      • L. Benini , L. Macchiarulo , A. Macii , M. Poncino . Layout-driven memory synthesis for embedded systems-on-chip. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 2 , 96 - 106
    4. 4)
      • Zivojnovic, V., Velarde, J., Schlager, C.: `DSPstone: a DSP-oriented benchmarking methodology', Int. Conf. on Signal Processing Applications and Technology, 1994.
    5. 5)
      • Panda, P.R., Dutt, N.D.: `High-level synthesis design repository', Proc. Int. Symp. on System Synthesis, 1995, p. 170–174(, .
    6. 6)
      • V. De La Luz , M. Kandemir , N. Vijaykrishnan , A. Sivasubramaniam , M.J. Irwin . Hardware and software techniques for controlling DRAM power modes. IEEE Trans. Comput. , 11 , 1154 - 1173
    7. 7)
      • 128/144-MBit Direct RDRAM Data Sheet. Rambus Inc., May 1999.
    8. 8)
      • De La Luz, V., Kandemir, M., Kolcu, I.: `Automatic data migration for reducing energy consumption in multi-bank memory systems', Proc. DAC, 2002, p. 213–218.
    9. 9)
      • Y.-H. Lu , L. Benini , G. De Micheli . Low power task scheduling for multiple devices. Int. Workshop on Hardware/Software Codesign , 39 - 43
    10. 10)
      • W.H. Press , S.A. Teukolsky , W.T. Vetterling , B.P. Flannery . (1994) Numerical recipes in C: the art of scientific computing.
    11. 11)
      • B.W. Kernighan , S. Lin . An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J.
    12. 12)
      • Benini, L., Macii, A., Poncino, M.: `A recursive algorithm for low-power memory partitioning', Int. Symp. Low Power Electronics and Design, 2000, p. 78–83.
    13. 13)
      • A. Sudarsanam , S. Malik . Simultaneous reference allocation in code generation for dual data memory bank ASIPs. ACM Trans. Des. Autom. Electron. Syst. , 2 , 242 - 264
    14. 14)
      • Fiduccia, C.M., Matteyses, R.M.: `A linear time heuristic for improving network partitions', Proc. of Design Automation Conf., 1982, p. 241–247.
    15. 15)
      • A.V. Aho , J.E. Hopcroft , J.D. Ullman . (1974) The design and analysis of computer algorithms.

Related content

This is a required field
Please enter a valid email address