Network-on-chip architectures and design methods

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Performance and power of gigascale systems-on-chip (SoCs) is increasingly communication-dominated. Designers have to accommodate the communication needs of an increasing number of integrated cores while preserving overall system performance under tight power budgets. State-of-the-art SoC communication architectures start facing scalability as well as modularity limitations, and more advanced bus specifications are emerging to deal with these issues at the expense of silicon area and complexity. Communication architecture evolutions mainly regard bus protocols (to better exploit available bandwidth) and bus topologies (to increase bandwidth). In the long run, more aggressive solutions are needed to overcome the scalability limitation, and networks-on-chip (NoCs) are currently viewed as a ‘revolutionary’ approach to provide a scalable, high performance and robust infrastructure for on-chip communication. The paper aims at surveying the evolution of the field, moving from SoC buses to forward-looking NoC research prototypes. The elements of continuity, as well as the key differences, will be captured, in an effort to extract general guiding principles in a fast-evolving domain.

Inspec keywords: multiprocessing systems; system-on-chip; logic design; system buses

Other keywords: bus protocols; bus topologies; network-on-chip architectures; network-on-chip design methods; state-of-the-art SoC communication architectures; gigascale systems-on-chip

Subjects: Multiprocessing systems; System buses; Digital circuit design, modelling and testing; Semiconductor integrated circuits; Microprocessors and microcomputers; Logic design methods; Microprocessor chips

References

    1. 1)
      • Boekhorst, F.: `Ambient intelligence, the next paradigm for consumer electronics: how will it affect silicon?', Proc. ISSCC 2002, February 2002, Vol. 1, p. pp. 28–31.
    2. 2)
      • ARM, AMBA Specification, v2.0, 1999.
    3. 3)
      • ARM, AMBA Multi-layer AHB overview, 2001.
    4. 4)
      • ARM, AMBA AXI Protocol Specification, 2003.
    5. 5)
      • Wodey, P., Camarroque, G., Barray, F., Hersemeule, R., Cousin, J.P.: `LO–TOS code generation for model checking of STBus based SoC: the STBus interconnection', Proc. ACM and IEEE Int. Conf. on Formal Methods and Models for Co-Design, June 2003, p. pp. 204–213.
    6. 6)
      • Sonics, Inc.: Sonics μNetworks. Technical Overview, 2002.
    7. 7)
      • Synopsys CoCentric. http://www.synopsys.com, 2004.
    8. 8)
    9. 9)
      • F. Poletti , D. Bertozzi , A. Bogliolo , L. Benini . Performance analysis of arbitration policies for SoC communication architectures. Des. Autom. Embedded Syst. , 8 , 189 - 210
    10. 10)
      • Loghi, M., Angiolini, F., Bertozzi, D., Benini, L., Zafalon, R.: `Analyzing on-chip communication in a MPSoC environment', Proc. IEEE Design Automation and Test in Europe Conf., (DATE04), February 2004, p. pp. 752–757.
    11. 11)
      • Henkel, J., Wolf, W., Chakradhar, S.: `On-chip networks: a scalable, communication-centric embedded system design paradigm', Proc. Int. Conf. on VLSI Design, January 2004, p. pp. 845–851.
    12. 12)
    13. 13)
      • Rijpkema, E., Goossens, K., Radulescu, A.: `Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip', Proc. Design Automation and Test in Europe, March 2003, p. pp. 350–355.
    14. 14)
      • K. Lee . (2004) A 51 mw 1.6 ghz on-chip network for low power heterogeneous SoC platform. ISSCC Digest of Tech. Papers.
    15. 15)
    16. 16)
      • Dally, W.J., Lacy, S.: `VLSI architecture: past, present and future', Conf. on Advanced Research in VLSI, 1999, p. pp. 232–241.
    17. 17)
      • D. Culler , J.P. Singh , A. Gupta . (1999) Parallel computer architecture, a hardware/software approach.
    18. 18)
    19. 19)
      • R. Tessier , W. Burleson . Reconfigurable computing and digital signal processing: a survey. J. VLSI Signal Process. , 3 , 7 - 27
    20. 20)
      • S. et al. Kumar . A network on chip architecture and design methodology. IEEE Symp. on VLSI 2002 , pp. 105 - 112
    21. 21)
      • Andriahantenaina, A., Charlery, H., Greiner, A., Mortiez, L.: `SPIN: a scalable, packet switched, on-chip micro-network', Proc. Design Automation and Test in Europe, March 2003, p. pp. 70–73.
    22. 22)
    23. 23)
      • Saastamoinen, I., Siguenza-Tortosa, D., Nurmi, J.: `Interconnect IP node for future systems-on-chip designs', Proc. IEEE Workshop on Electronic Design, Test and Applications, January 2002, p. pp. 116–120.
    24. 24)
      • Dall'Osso, M., Biccari, G., Giovannini, L., Bertozzi, D., Benini, L.: `Xpipes: a latency insensitive parameterized network-on-chip architecture for multi-processor SoCs', Proc. ICCD 2003, October 2003, p. pp. 536–539.
    25. 25)
      • Jalabert, A., Murali, S., Benini, L., De Micheli, G.: `XpipesCompiler: a tool for instantiating application specific networks on chip', Proc. DATE 2004, 2004, p. pp. 884–889.
    26. 26)
      • Agarwal, V., Hrishikesh, M.S., Keckler, S.W., Burger, D.: `Clock rate versus IPC: the end of the road for conventional microarchitectures', Proc. Int. Symp. Computer Architecture, June 2000, p. pp. 248–250.
    27. 27)
      • L.P. Carloni , K.L. McMillan , A.L. Sangiovanni Vincentelli . Theory of latency-insensitive design. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., September , 9 , 1059 - 1076
    28. 28)
      • ITRS 2001. http://public.itrs.net/Files/2001ITRS/Home.htm.
    29. 29)
      • P. Glaskowsky . Pentium4 (partially) previewed. Microprocess. Rep. , 8 , 10 - 13
    30. 30)
      • J. Duato , S. Yalamanchili , L.M. Ni . (2003) Interconnection networks: an engineering approach.
    31. 31)
      • VSI Alliance: Virtual Component Interface Standard 2000.
    32. 32)
      • OCP International Partnership, Open Core Protocol Specification, 2001.
    33. 33)
    34. 34)
      • Muttersbach, J., Villiger, T., Kaeslin, H., Felber, N., Fichtner, W.: `Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems', IEEE ASIC/SOC Conf., September 1999, p. pp. 317–321.
    35. 35)
      • S.J. Lee . An 800 MHz star-connected on-chip network for application to systems on a chip. ISSCC Digest of Tech. Papers , 468 - 469
    36. 36)
      • S. Murali , G. De Micheli . SUNMAP: a tool for automatic topology selection and generation for NoCs. Proc. Des. Autom. Conf. , 914 - 919
    37. 37)
      • E.B. Van der Tol , E.G.T. Jaspers . Mapping of MPEG4 decoding on a flexible architecture platform. Proc. SPIE-Int. Soc. Opt. Eng. , 1 - 13
    38. 38)
      • D. Bertozzi , A. Jalabert , S. Murali , R. Tamhankar , S. Stergiou , L. Benini , G. De Micheli . NoC synthesis flow for customized domain specific multiprocessor systems-on-Chip. IEEE Trans. Parallel Distrib. Syst.
    39. 39)
      • Wang, H.S.: `Orion: A power-performance simulator for interconnection networks', Proc. IEEE/ACM Int. Symp. on Microarchitecture, Nov. 2002, Istanbul, Turkey, p. 294–305.
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