Network-on-chip architectures and design methods

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Performance and power of gigascale systems-on-chip (SoCs) is increasingly communication-dominated. Designers have to accommodate the communication needs of an increasing number of integrated cores while preserving overall system performance under tight power budgets. State-of-the-art SoC communication architectures start facing scalability as well as modularity limitations, and more advanced bus specifications are emerging to deal with these issues at the expense of silicon area and complexity. Communication architecture evolutions mainly regard bus protocols (to better exploit available bandwidth) and bus topologies (to increase bandwidth). In the long run, more aggressive solutions are needed to overcome the scalability limitation, and networks-on-chip (NoCs) are currently viewed as a ‘revolutionary’ approach to provide a scalable, high performance and robust infrastructure for on-chip communication. The paper aims at surveying the evolution of the field, moving from SoC buses to forward-looking NoC research prototypes. The elements of continuity, as well as the key differences, will be captured, in an effort to extract general guiding principles in a fast-evolving domain.

Inspec keywords: multiprocessing systems; system-on-chip; logic design; system buses

Other keywords: bus protocols; bus topologies; network-on-chip architectures; network-on-chip design methods; state-of-the-art SoC communication architectures; gigascale systems-on-chip

Subjects: Multiprocessing systems; System buses; Digital circuit design, modelling and testing; Semiconductor integrated circuits; Microprocessors and microcomputers; Logic design methods; Microprocessor chips

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