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System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms

System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms

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Current and future system-on-chip (SoC) designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility, performance and cost constraints. Such a heterogeneous multiprocessor SoC architecture has enormous potential for optimisation, but requires a system-level design environment and methodology to evaluate architectural alternatives. A methodology is proposed to jointly design and optimise the processor architecture together with the onchip communication based on the LISA processor design platform in combination with SystemC transaction level models. The proposed methodology advocates a successive refinement flow of the system-level models of both the processor cores and the communication architecture. This allows design decisions based on the best modelling efficiency, accuracy and simulation performance possible at the respective abstraction level. The effectiveness of our approach is demonstrated by the exemplary design of a dual-processor JPEG decoding system.

References

    1. 1)
      • Kogel, T., Doerper, M., Wieferink, A.: `A modular simulation framework for architectural exploration of on-chip interconnection networks', IEEE/ACM/IFIP Int. Conf. on HW/SW Codesign and System Synthesis, Newport Beach, CA, USA, 2003.
    2. 2)
      • Braun, G., Wieferink, A., Schliebusch, O.: `Processor/memory co-exploration on multiple abstraction levels', Presented at Design Automation & Test in Europe (DATE), 2003, Munich, Germany.
    3. 3)
      • ‘ConvergenSC’, CoWare, http://www.coware.com.
    4. 4)
      • Rijpkema, E., Goossens, K.G.W., Radulescu, A.: `Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip', Proc. Int. Conf. on Design, Automation and Test in Europe (DATE), 2003.
    5. 5)
      • ‘CoCentric System Studio’, Synopsys, http://www.synopsys.com.
    6. 6)
      • Cochrane, A., Lennard, C., Topping, K., et al.: ‘AMBA AHB cycle level interface (AHB CLI) specification’, 2003.
    7. 7)
      • A. Hoffmann , T. Kogel , A. Nohl , G. Braun , O. Schliebusch , O. Wahlen , A. Wieferink , H. Meyr . A novel methodology for the design of application specific instruction-set processor using a machine description language. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 11 , 1338 - 1354
    8. 8)
      • Haverinen, A., Leclercq, M., Weyrich, N., and Wingard, D.: ‘White Paper for SystemC based SoC communication modeling for the OCP protocol’, http://www.ocpip.org/data/systemc.pdf, 2003.
    9. 9)
      • Rowson, J.A., Sangiovanni-Vincentelli, A.: `Interface-based design', Proc. Design Automation Conf. (DAC), 1997.
    10. 10)
      • T. Grotker , S. Liao , G. Martin , S. Swan . (2002) System design with SystemC.
    11. 11)
      • Nohl, A., Braun, G., Hoffmann, A.: `A universal technique for fast and flexible instruction-set architecture simulation', Proc. Design Automation Conf. (DAC), New Orleans, USA, 2002.
    12. 12)
      • Notbauer, J., Albrecht, T., Niedrist, G., Rohringer, S.: `Verification and management of a multimillion-gate embedded core design', Proc. Design Automation Conf. (DAC), 1999.
    13. 13)
      • Mishra, P., Grun, P., Dutt, N., Nicolau, A.: `Processor-memory co-exploration driven by an architectural description language', Int. Conf. on VLSI Design, 2001.
    14. 14)
      • Cesario, W., Baghdadi, A., Gauthier, L.: `Component-based design approach for multicore SoCs', Proc. Design Automation Conf. (DAC), 2002.
    15. 15)
      • ‘SystemC initiative’, http://www.systemc.org.
    16. 16)
      • Schliebusch, O., Chattopadhyay, A., Steinert, M.: `RTL processor synthesis for architecture exploration and implementation', Presented at Conf. on Design, Automation & Test in Europe (DATE), Paris, France, 2004.
    17. 17)
      • Kogel, T., Wieferink, A., Leupers, R.: `Virtual architecture mapping: a SystemC based methodology for architectural exploration of system-on-chip designs', Int. Workshop on Systems, Architecture, Modeling and Simulation (SAMOS), 2003, Samos, Greece.
    18. 18)
      • Paulin, P., Magarshack, P.: `System-on-chip beyond the nanometer wall', Proc. Design Automation Conf. (DAC), 2003.
    19. 19)
      • Hines, K., Borriello, G.: `Dynamic communication models in embedded system co-simulation', Proc. Design Automation Conf., (DAC), 1997.
    20. 20)
      • Leupers, R.: `HDL-based modeling of embedded processor behavior for retargetable compilation', Proc. Int. Symp. on System Synthesis (ISSS), 1998.
    21. 21)
      • Ogawa, O., Shinohara, K., Watanabe, Y.: `A practical approach for bus architecture optimization at transaction level', Proc. Designers' Forum, Int. Conf. on Design, Automation and Test in Europe (DATE), 2003.
    22. 22)
      • Wieferink, A., Kogel, T., Nohl, A.: `A generic toolset for SoC multiprocessor debugging and synchronisation', IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP), The Hague, The Netherlands, 2003.
    23. 23)
      • G. Hadjiyiannis , S. Devadas . Techniques for accurate performance evaluation in architecture exploration. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 601 - 615
    24. 24)
      • ‘LISATek Product Line’, CoWare, http://www.coware.com.
    25. 25)
    26. 26)
      • Fauth, A., Van Praet, J., Freericks, M.: `Describing instruction set processors using nML', Proc. European Design and Test Conference (ED&TC), 1995.
    27. 27)
      • Guerra, L., Fitzner, J., Talukdar, D.: `Cycle and phase accurate DSP modeling and integration for HW/SW co-verification', Proc. Design Automation Conf. (DAC), 1999.
    28. 28)
      • Wieferink, A., Doerper, M., Kogel, T.: `Early ISS integration into network-on-chip designs', Presented at Int. Workshop on Systems, Architectures, Modeling and Simulation (SAMOS), 2004, Samos, Greece.
    29. 29)
      • ‘Official JPEG homepage’, http://www.jpeg.org.
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