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System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms

System level processor/communication co-exploration methodology for multiprocessor system-on-chip platforms

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Current and future system-on-chip (SoC) designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility, performance and cost constraints. Such a heterogeneous multiprocessor SoC architecture has enormous potential for optimisation, but requires a system-level design environment and methodology to evaluate architectural alternatives. A methodology is proposed to jointly design and optimise the processor architecture together with the onchip communication based on the LISA processor design platform in combination with SystemC transaction level models. The proposed methodology advocates a successive refinement flow of the system-level models of both the processor cores and the communication architecture. This allows design decisions based on the best modelling efficiency, accuracy and simulation performance possible at the respective abstraction level. The effectiveness of our approach is demonstrated by the exemplary design of a dual-processor JPEG decoding system.

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