Unified SOC test approach based on test data compression and TAM design

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Unified SOC test approach based on test data compression and TAM design

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Test access mechanism (TAM) optimisation and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time both these approaches into a single test methodology. We show how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on test data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.

Inspec keywords: integrated circuit testing; logic testing; system-on-chip

Other keywords: integrated test; test data volume reduction; single test methodology; TAM optimisation; unified SOC test approach; testing time; test resource requirements; test data compression; test access mechanism; test application time; test pin overheads

Subjects: Logic design methods; Digital circuit design, modelling and testing; Semiconductor integrated circuit design, layout, modelling and testing

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