Energy-delay efficient filter cache hierarchy using pattern prediction scheme

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Energy-delay efficient filter cache hierarchy using pattern prediction scheme

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Filter cache (FC) is an auxiliary cache much smaller than the main cache. The FC is closest in hierarchy to the instruction fetch unit and it must be small in size to achieve energy-efficient realisations. A pattern prediction scheme is adapted to maximise energy savings in the FC hierarchy. The pattern prediction mechanism proposed relies on the spatial hit or miss pattern of the instruction access stream over previous FC line accesses. Unlike existing techniques, which make predominantly incorrect hit predictions, the proposed approach aims to minimise this, thereby reducing the performance and power penalties associated with it. Simulation results on an extensive set of multimedia benchmarks are presented as proof of its efficacy. The prediction technique results in energy-delay savings of up to 6.8% over the NFPT predictor, which has been proposed in the past as the preferred prediction scheme for FC structures. Investigations conclusively demonstrate that the performance of the proposed prediction scheme is comparable with and in most cases better than that based on NFPT. Unlike NFPT, the new proposed prediction technique lends well for VLSI efficient implementation, making it the preferred choice for energy aware implementations.

Inspec keywords: memory architecture; cache storage; VLSI; instruction sets; prediction theory

Other keywords: instruction fetch unit; filter cache hierarchy; energy-delay; pattern prediction scheme; energy-efficient realisation; energy aware implementation; VLSI efficient implementation; NFPT predictor

Subjects: Semiconductor integrated circuits; Memory circuits; Storage system design; Semiconductor storage

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