Built-in self-repair techniques for embedded RAMs

Built-in self-repair techniques for embedded RAMs

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An efficient built-in self-repair approach, column-block-level reconfiguration methodology, is proposed. It is based on the concept of divided bit-line (DBL) for high-capacity memories including SRAMs and DRAMs, widely used in low-power memory designs. However, the inherent characteristics (two or more memory cells are combined together to divide the bit-line into several sub bit-lines) of divided bit-line memories have not been used for fault-tolerant applications. Therefore the column_block_repair (CBR) fault-tolerant architecture is proposed based on the structure of DBL for high-capacity memories. The redundant columns of a memory array are divided into column blocks and reconfiguration is performed at the column block level instead of the traditional column level. The fault-tolerant architecture can improve the yield for memory fabrication significantly. Moreover, the characteristics of low power and fast access time of DBL memories are also preserved. The reconfiguration mechanism of the CBR architecture requires negligible hardware overhead. According to experimental results, the hardware overheads are less than 0.58% and 0.012% for 256-Kbit SRAMs and 8-Mbit DRAMs, respectively. The repair rate of the approach is compared with previous memory repair algorithms. It is found that the CBR approach improves the repair rate significantly. The yield improvement over traditional column-based approaches is also analysed. Simulated results show that the present approach can significantly improve fabrication yield.


    1. 1)
      • Erso (Lin, M.K.): ‘1997 semiconductor industry annual report’. ITRS project report, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, June 1997.
    2. 2)
      • Moore, G.E.: `Progress in digital integrated electronics', Proc. IEEE Int. Electron Devices Meet., 1975, San Jose, CA, p. 11–13.
    3. 3)
      • C.T. Huang , J.R. Huang , C.F. Wu , C.W. Wu , T.Y. Chang . A programmable BIST core for embedded DRAM. IEEE Des. Test Comput. , 59 - 70
    4. 4)
      • A.J. Goor , Van de . (1996) Testing semiconductor memories – theory and practice.
    5. 5)
    6. 6)
      • M. Franklin , K.K. Saluja . Embedded RAM testing. Proc. IEEE Int. Workshop on Memory technology, design and testing, San Jose, CA , 29 - 33
    7. 7)
    8. 8)
      • Nakahara, S., Higeta, K., Kohno, M., Kawamura, T., Kakitani, K.: `Built-in self test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm', Proc. Int. Test Conf., October 1999, Washington, DC, p. 301–310.
    9. 9)
      • Zarrineh, K., Upadhyaya, J.: `On programmable memory built-in self-test architectures', Proc. of IEEE Conf. on Design, automation and test in Europe, Munich, Mar. 1999, p. 708–713.
    10. 10)
      • M. Sachdev . (1998) Defect-oriented testing for CMOS analog and digital circuits.
    11. 11)
      • Mazumder, P., Yih, J.S.: `A novel built-in self-repair approach to VLSI memory yield enhancement', Proc. of Int. Test Conf., October 1990, Washington, DC, p. 833–841.
    12. 12)
      • Kim, I., Zorian, Y., Komoriya, G., Pham, H., Higgins, F.P., Lewandowski, J.L.: `Built in self repair for embedded high-density SRAM', Proc. Int. Test Conf., October 1998, Washington, DC, p. 1112–1119.
    13. 13)
      • M. Hpriguchi , J. Etoh , M. Aoki , K. Itoh , T. Matsumoto . A flexible redundancy technique for high-density DRAM's. IEEE J. Solid-State Circuits , 1 , 12 - 17
    14. 14)
      • Kim, H.C., Yi, D.S., Park, J.Y., Cho, C.H.: `A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies', Proc. Int. Conf. on VLSI and CAD, Oct. 1999, Seoul, p. 602–605.
    15. 15)
      • R. Treuer , V.K. Agrawal . Built-in self diagnosis for repairable embedded RAMs. IEEE Design Test Comput. , 24 - 33
    16. 16)
      • S.Y. Kuo , W.K. Fuchs . Efficient spare allocation in reconfigurable arrays. IEEE Design Test Comput. , 24 - 31
    17. 17)
      • Schober, V., Paul, S., Picot, O.: `Memory built-in self repair using redundant words', Proc. Int. Test Conf., October 2001, Washington, DC, p. 995–1001.
    18. 18)
      • Nelson, E., Dreibelbis, J.: `Test and repair of large embedded DRAMs: Part 2', Proc. Int. Test Conf., October 2001, Washington, DC, p. 173–181.
    19. 19)
      • Karandikar, A., Parhi, K.K.: `Low-power SRAM design using hierarchical divided bit-line approach', Proc. Int. Conf. on Computer design, Oct. 1998, Austin, TX, p. 82–88.
    20. 20)
      • B. Prince . (1997) Semiconductor memories: a handbook of design, manufacture, and application.
    21. 21)
      • M. Yoshimoto , K. Anami , H. Shinohara , T. Yoshihara , H. Takagi , S. Nagao , S. Kayano , T. Nakano . A divided word-line structure in static RAM and its application to a 64K full CMOS RAM. IEEE J. Solid-State Circuits , 5 , 479 - 485
    22. 22)
    23. 23)
      • K.J. Schultz , R.G. Gibbins , J.S. Fujimoto , R.S. Philips , G.F.R. Gibson , A.L. Silburt . Low-supply-noise low-power embedded modular SRAM. IEEE Proc., Circuits, Devices Syst. , 73 - 82
    24. 24)
      • M. Margala . Low-power SRAM circuit design. Memory Technol., Design Test , 115 - 122
    25. 25)
      • J.E. Price . A new look at yield of integrated circuits. Proc. IEEE , 8 , 1290 - 1291
    26. 26)
      • B.W. Johnson . (1989) Design and analysis of fault-tolerant digital system.
    27. 27)

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