Probabilistic carry state estimate for improved asynchronous adder performance
The paper presents a new type of simple adder, suitable for asynchronous digital circuits and implementation in VLSI technology, which has either speed and/or area advantages over existing designs. It is based on the concept of predicting the carry from least to most significant halves of a 32 or 64 bit adder in such a way that it has a high probability of being correct, while introducing only a low area overhead from the required early completion control circuitry. Detailed design and simulation of the adder at the gate level is presented, together with its evaluation by comparing detailed performance with equivalent ripple, carry lookahead, and carry select designs. Since the objective is improved asynchronous circuits, it is average rather than worst-case delays that are the significant measures. In comparison to other adder networks it is demonstrated that by using the important metrics of area, speed and delay–area product the proposed adder can outperform the 32 bit and 64 bit adders cited in the literature. Delay–area product results show that the proposed approach gives a saving of over 14% and 24% on the carry-select lookahead schemes for 32 bit and 64 bit adders respectively.
