Boolean or switching equations are powerful mathematical tools for digital logic. Several problems in digital circuit design, such as automatic test pattern generation, could be efficiently solved if fast procedures for solving Boolean equations were available. Several methods for solving this class of equations have been developed, but their efficiency is a problem. A new formulation for the computation of Boolean operations based on cubic representation of Boolean functions, termed the cube set method, is presented. The solutions provided by this approach are given as a set of cubes satisfying the disjoint property. Some definitions and theorems are given to describe the method and experimental results are presented.
References
-
-
1)
-
Y. WANG ,
C. M
.
Solving Boolean equations using ROSOP forms.
IEEE Trans.
,
2 ,
171 -
177
-
2)
-
MALIK, S., WANG, A., BRAYTON, R., SANGIOVANNI-VINCENTELLI, A.: `Logic verification using binary decision diagrams in logic synthesis environment', Design Automation Conference, 1988, p. 624–628.
-
3)
-
W. DEL PICCHIA
.
A numerical algorithm for the resolution for Boolean equations.
IEEE Trans.
,
983 -
986
-
4)
-
KOZLOWSKI, T., DAGLESS, E.L., SAUL, J.M.: `An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions', Proceedings of IEEE International Conference on Computer design (ICCD'95), 1995, p. 244–249.
-
5)
-
P.R. BHATTACHARJEE ,
S.K. BASU ,
J.C. PAUL
.
Translation of the problem of complete test set generation to pseudo-Boolean programming.
IEEE Trans.
,
7 ,
864 -
867
-
6)
-
R.T. STANION ,
A.D. BHATTACHARY ,
C. SECHEN
.
An efficient method for generating exhaustive test sets.
IEEE Trans.
,
12 ,
1516 -
1525
-
7)
-
R.K. BRAYTON ,
G.D. HACHTEL ,
C.T. M ,
A.L. SANGIOVANNI-VINCENTELLI
.
(1984)
, Logic minimization algorithms for VLSI synthesis.
-
8)
-
S. RUDEANU
.
(1974)
, Boolean functions and equations.
-
9)
-
B. KRISHNAMURTHY ,
J.G. TOLLIS
.
Improved techniques for estimating signal probabilities.
IEEE Trans.
,
7 ,
1041 -
1045
-
10)
-
CHAI, L.: `ESOP circuit minimization based on the function ON-set', Master's Thesis, 2000.
-
11)
-
P. STEPHAN ,
R.K. BRAYTON ,
A.L. SANGIOVANNI-VINCENTELLI
.
Combinational test generation using satisfiability.
IEEE Trans.
,
9 ,
1167 -
1176
-
12)
-
G. BOOLE
.
(1854)
, An investigation of the laws of thought.
-
13)
-
R. JAIN
.
(1991)
, The art of computer systems performance analysis.
-
14)
-
S. RUDEANU
.
An algebraic approach to Boolean equations.
IEEE Trans.
,
206 -
207
-
15)
-
RUDELL, R.: `Dynamic variable ordering for ordered binary decision diagrams', International Conference on Computer-aided-design, 1993, p. 42–47.
-
16)
-
I. WEGENER
.
The size of reduced OBDD's and optimal read-once branching programs for almost all Boolean functions.
IEEE Trans.
,
11 ,
1262 -
1269
-
17)
-
S. SVOBODA
.
An algorithm for solving Boolean equations.
IEEE Trans.
,
557 -
559
-
18)
-
P. TRABADO ,
A. LLORIS-RUIZ ,
J. ORTEGA-LOPERA
.
Solution of switching equations based on a tabular algebra.
IEEE Trans.
,
5 ,
591 -
596
-
19)
-
MERCER, M., KAPUR, R., ROSS, D.: `Functional approaches to generating orderings for efficient symbolic representation', 29th Design Automation Conference, 1992, p. 40–45.
-
20)
-
R. BRYANT
.
Graph-based algorithm for Boolean function manipulation.
IEEE Trans.
,
8 ,
677 -
691
-
21)
-
S. UNGER
.
Some additions to `Solution of switching equations based on a tabular algebra.
IEEE Trans.
,
3 ,
365 -
367
-
22)
-
BULTER, K.M., ROSS, D.E., KAPUR, R., MERCER, M.R.: `Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams', 28th Design Automation Conference, 1991, p. 417–420.
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cdt_20010706
Related content
content/journals/10.1049/ip-cdt_20010706
pub_keyword,iet_inspecKeyword,pub_concept
6
6