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Completion-detecting carry select addition

Completion-detecting carry select addition

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Logic analysis, circuit implementation and verification of a novel self-timed adder scheme based on carry select (CS) logic are presented. The preliminary analysis of the variable-time behaviour of CS logic justifies the design of self-timed CS adders, and identifies the best choice for the block size to optimise the average performance. The logic design and full-custom circuit implementation is described of a completion-detecting CS adder by means of precharged CMOS logic. The correct asynchronous operation of the circuit is verified by means of layout level SPICE simulation referring to a 0.35 μm CMOS process. The worst-case addition time is comparable with the fastest fixed-time adders, which is a considerable result for a completion-detecting technique. The hardware overhead can be limited to 23% over a conventional CS adder. SPICE simulation estimates an average detected addition time of 1.6 ns for a 64 bit adder, including the precharge time.

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