Power consumption has become a great concern for IC and system designs. As a consequence, power-driven technology mapping has attracted several pieces of research. However, the power model they used cannot properly capture the power dissipation when the output of a gate does not switch. In this paper, we propose a pattern-oriented power modelling for improved technology mapping. We first perform a profitability study using the complete pattern to pattern transition data organised in tabular form. Then, we propose a probability-based, pattern-oriented technology mapping method. Empirical results on benchmark circuits demonstrate that the proposed method delivered an average of 13% power reduction compared with the traditional mapping method.
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