Systolic dual basis serial multiplier

Access Full Text

Systolic dual basis serial multiplier

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IEE Proceedings - Computers and Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The paper presents a systolic serial dual basis multiplier for the Galois field GF(2m) which is based on the Berlekamp-like multiplication algorithm. It needs only one control signal and is easy to simplify for the field which is generated by the irreducible polynomial xm + x + 1. The multiplier's architecture is highly regular, modular and easily expandable, hence it is suitable for implementation using VLSI technologies.

Inspec keywords: systolic arrays; VLSI; polynomials

Other keywords: control signal; VLSI technologies; Galois field; Berlekamp-like multiplication algorithm; multiplier's architecture; irreducible polynomial; systolic dual basis serial multiplier

Subjects: Interpolation and function approximation (numerical analysis); Parallel architecture; Semiconductor integrated circuits; Interpolation and function approximation (numerical analysis); Logic circuits; Logic and switching circuits

References

    1. 1)
      • B. Hochet , P. Quinton , R. Yves . Systolic Gaussian elimination over GF(p) with partialpivoting. IEEE Trans. Comput. , 9 , 1321 - 1324
    2. 2)
      • Diab, M.: `Systolic architectures for multiplication over finite field GF(2', 8th international conference AAECC-8, August 1990, Tokyo, Japan, p. 329–340.
    3. 3)
      • P. Quinton , Y. Robert . (1989) Algorithmes et architectures systoliques.
    4. 4)
      • S.T.J. Fenn , M. Benaissa , D. Taylor . GF(2m) multiplication and division over the dual basis. IEEE Trans. Comput. , 3 , 319 - 327
    5. 5)
      • R.J. Webb . (1988) Digital technology with MOS integrated circuits.
    6. 6)
      • R.J. McEliece . (1987) Finite fields for computer scientists and engineers.
    7. 7)
      • R. Lidl , H. Niederreiter . (1986) An introduction to finite fields and their applications.
    8. 8)
      • S.T.J. Fenn , M. Benaissa , D. Taylor . Bit serial Berlekamp-like multipliers for GF(2m). Electron. Lett. , 22 , 1893 - 1894
    9. 9)
      • M. Diab , A. Poli . New bit-serial systolic multiplier for GF(2m) using irreducible trinomials. Electron. Lett. , 13 , 1183 - 1184
    10. 10)
      • S.T.J. Fenn , D. Taylor , M. Benaissa . A dual basis bit-serial systolic multiplier for GF(2m). Integr., VLSI J. , 139 - 149
    11. 11)
      • S.T.J. Fenn , D. Taylor , M. Benaissa . A dual basis systolic multiplier for GF(2m). IEE Proc.- Comput. Digit. Tech. , 1 , 43 - 46
    12. 12)
      • E.R. Berlekamp . Bit-serial Reed-Solomon encoders. IEEE Trans. , 6 , 869 - 874
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cdt_19981938
Loading

Related content

content/journals/10.1049/ip-cdt_19981938
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading