Optimisation is a key facet of the behavioural synthesis problem. The process may be carried out at different levels in the processing, usually at the source or datapath levels, or both. In a previous paper, the authors reported a source level VHDL optimiser which applies optimisation techniques derived from conventional sequential and parallel programming languages. This process produces structural descriptions that are up to 33% faster and 20% smaller than the corresponding ‘brute force’ mapping of behaviour to structure. In the paper the authors describe a further set of optimisation transforms that may be applied at the source level to a VHDL behavioural description. These transforms have no conventional programming language counterpart, and are specific to hardware description languages. A number of designs have been optimised with respect to area and/or delay, with and without these transforms. The results show that with this extra class of transforms there is an improvement of ~44% in delay and 38% in area.
References
-
-
1)
-
Walker, R.A., Thomas, T.E.: `Behavioural level transformation in the CMU-DA system', IEEE 20th Design automation conference, 1983, p. 788–789.
-
2)
-
A.D. Brown ,
K.R. Baker
.
Asynchronous dead area test in synthesized systems.
IEEE Trans. Comput.-Aided Des.
-
3)
-
S. Kirkpatrick
.
Optimisation by simulated annealing: quantitative studies.
J. Stat. Phys.
,
975 -
986
-
4)
-
Ferrante, J., Mace, M.: `On linearizing parallel code', 12th ACM symposium on Principles of programming languages, 1985, p. 179–189.
-
5)
-
Bushnell, M.L., Director, S.W.: `Ulysses: An expert system based VLSI design environment', Proceedings of IEEE conference, ISCAS, 1985, p. 279–287.
-
6)
-
D. Padua ,
M. Wolfe
.
Advanced compiler optimisations for supercomputers.
Commun. ACM
,
22 ,
1184 -
1201
-
7)
-
J. Bhasker
.
Implementation of an optimizing compiler for VHDL.
Sigplan Not.
,
92 -
103
-
8)
-
K.R. Baker ,
A.D. Brown ,
A.J. Currie
.
Optimization efficiency in behavioral synthesis.
IEE Proc. E
,
5 ,
399 -
406
-
9)
-
T.P.K. Nijhar ,
A.D. Brown
.
Source level optimisation of VHDL for behavioural synthesis.
IEE Proc. Comput. Digit. Tech.
,
1
-
10)
-
M.E. Wolfe ,
M.S. Lam
.
A loop transformation theory to maximise parallelism.
IEEE Trans. Parallel Distrib. Syst.
,
4 ,
452 -
471
-
11)
-
N. Audsley ,
A. Burns ,
R. Davis ,
K.W. Tindell ,
A.J. Wellings
.
Fixed priority pre-emptive scheduling – anhistorical perspective.
Real-Time Syst.
,
173 -
198
-
12)
-
J. Ferrante ,
K. Ottenstein ,
J. Warren
.
The program dependence graph and its use in optimisation.
ACM Trans. Program. Lang. Syst.
,
4 ,
319 -
349
-
13)
-
G.D. Micheli ,
D. Ku ,
F. Mailhot ,
T. Truong
.
The Olympus synthesis system.
IEEE Des. Test Comput.
,
37 -
53
-
14)
-
J.S. Snyder ,
D.B. Whalley ,
T.P. Baker
.
Fast context switches, compiler and architectural support for pre-emptivescheduling.
Microprocess. Microsyst.
,
1 ,
35 -
42
-
15)
-
Baker, K.R.: `Multiple objective optimisation of data in a behavioural synthesis system', 1992, PhD, University of Southampton.
-
16)
-
Peng, Z.: `Synthesis of VLSI systems with the CAMAD design aid', Proceedings of the 23rd DAC, 1986, Las Vegas, NV, USA, p. 278–284.
-
17)
-
F. Brewer ,
D. Gajski
.
Chippe: A system for constraint driven behavioural synthesis.
IEEE Trans.
,
7 ,
681 -
695
-
18)
-
K.R. Baker ,
A.J. Currie ,
K.G. Nichols
.
Multiple objective optimization in a behavioral synthesis system.
IEE Proc. E
,
4 ,
253 -
260
-
19)
-
H. Zima ,
B. Chapman
.
(1991)
Supercompilers for parallel and vector computers.
-
20)
-
A. Alfred ,
S. Ravi ,
U. Jeffrey
.
(1986)
Compilers, principles, techniques, and tools.
-
21)
-
A. Rushton
.
(1995)
VHDL for logic synthesis.
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cdt_19971118
Related content
content/journals/10.1049/ip-cdt_19971118
pub_keyword,iet_inspecKeyword,pub_concept
6
6