Stochastic model of a cache-coherency overhead in SCI rings

Stochastic model of a cache-coherency overhead in SCI rings

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The authors present a new analytical performance model of the IEEE P1596 Standard Coherent Interface, which is a distributed cache-coherency protocol for shared-memory multiprocessors. The paper focuses upon an implementation of the protocol on a unidirectional ring architecture (the ‘default’ architecture for SCI systems). The authors identify the possible memory and cache-line states and corresponding processor actions for a memory access, and derive the equilibrium line state probabilities by solving a Markov model expressed as a set of fixed-point equations. The probabilities of a processor performing a particular action then follow, from which the message transmission profile for each processor is derived. These traffic equations are then fed into an M/G/1 model for the ring architecture, in which the ring traffic at a node has priority over traffic originating in that node. Further analysis then leads to the mean message transmission time, and hence the mean memory access time and processor utilisation. The application of the model is illustrated by undertaking a performance comparison of two alternative node architectures and report some numerical results are reported for various parameterisations.


    1. 1)
      • ‘IEEE P1596 Standard Specification’. IEEE, 1989.
    2. 2)
      • S. Gjessing , D.B. Gustavson , J.R. Goodman , D.V. James , E.H. Kristiansen , M. Dubois , S. Thakkar . (1992) The SCI cache coherence protocol, Scalable shared memory multiprocessors.
    3. 3)
      • Spiers, B. and Wiggers H.: ‘Performance analysis ofSCI cachecoherency protocol’. IEEEP1956, doc124, 1989.
    4. 4)
      • D.V. James , M. Dubois , S. Thakkar . (1990) SCI cache coherence, Cache and interconnect architectures in multiprocessors.
    5. 5)
      • Hexsel, R., Topham, N.: `Performance of SCI memory hierarchies', Proceedings of the8th international workshop on Support for large-scale memory architectures, April 1994.
    6. 6)
      • Singh, J.P., Weber, W.-D., Goopta, A.: `Stanford parallel applications for shared memory', CSL-TR-91-469, Technical report, 1991.
    7. 7)
      • (1994) Mathematica - A system for doing mathematics by computer.
    8. 8)
      • Scott, S.L., Goodman, J.R., Vernon, M.K.: `Performance of the SCI ring', Proceedings of the19th annual international symposium on Computer architecture, May 1992.
    9. 9)
      • Greenberg, A.G., Mitrani, I.: `Analysis of snooping caches', Proceedings of Performance 87, 12thinternational symposium on Computer performance, December 1987, Brussels.
    10. 10)
      • Ametistova, E., Mitrani, I.: `Modelling and evaluation of cache coherence protocols inmultiprocessor systems', Proceedings of the 9th UK Performance engineering workshop, 1993, Loughborough.
    11. 11)
      • T.M. Cole, Private communication, 1994.
    12. 12)
      • J.W. Bothner , T.I. Hulaas . Various Interconnects for SCI-based systems.
    13. 13)
      • Agarwal, A., Simoni, R., Hennessy, J., Horowitz, M.: `An evaluation of directory schemesfor cache coherence', Proceedings of the 15th annual international symposium on Computerarchitecture, June 1988, p. 280–289.
    14. 14)
      • Lenoski, D., Laudon, J., Gharachorloo, K., Gupta, A., Hennessy, J.: `The directory-based cache coherence protocol for the DASH multiprocessor', Proceedings of the 17th annual international symposium on Computer architecture, June 1990.
    15. 15)
      • A. Gupta , W.-D. Weber , T. Mowry . Reducing memory and traffic requirements for scalabledirectory-based cache coherence systems.
    16. 16)
      • L. Censier , P. Feutrier . A new solution to coherence problems in multicache systems. IEEE Trans. Comput. , 12 , 112 - 118
    17. 17)
      • P.G. Harrison , N.M. Patel . (1993) Performance modelling of communication networks and computer architectures.
    18. 18)
      • Saulsbury, A., Wilkinson, T., Carter, J., Landin, A.: `An argument for simple COMA', First IEEE symposium on High performance computer architecture, January 1995, Rayleigh, North Car., USA, p. 276–285.

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