QCA memory with parallel read/serial write: design and analysis

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QCA memory with parallel read/serial write: design and analysis

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The authors present a novel memory architecture for quantum-dot cellular automata (QCA). The proposed architecture combines the advantage of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory, hence its name is ‘hybrid’. This hybrid architecture utilises a novel arrangement in the addressing circuitry of the QCA loop for implementing the memory-in-motion paradigm. An evaluation of latency and area is pursued. It is shown that while for a serial memory, latency is O(N) (where N is the number of bits in a loop), a constant latency is accomplished in the hybrid memory. For area analysis, a novel characterisation that considers cells in the logic circuitry, interconnect in addition to the unused portion of the Cartesian plane (i.e. the whole geometric area encompassing the QCA layout), is proposed. This is referred to as the effective area. Different layouts of the hybrid memory are proposed to substantiate the reduction in effective area.

Inspec keywords: logic design; semiconductor storage; integrated circuit layout; cellular automata; memory architecture; quantum dots

Other keywords: serial memory; memory-in-motion paradigm; hybrid memory architecture; parallel memory; parallel read/serial write; QCA memory; quantum-dot cellular automata; logic circuitry; Cartesian plane

Subjects: Digital circuit design, modelling and testing; Memory circuits; Semiconductor storage; Semiconductor integrated circuit design, layout, modelling and testing; Logic design methods

References

    1. 1)
      • Walus, K., Vetteth, A., Jullien, G.A., Dimitrov, V.S.: `RAM design using quantum-dot cellular automata', Technical Proc. 2003 Nanotechnology Conf. and Trade Show, March 2003, 2, p. 160–163.
    2. 2)
      • Frost, S.E., Rodrigues, A.F., Janiszewski, A.W., Rausch, R.T., Kogge, P.M.: `Memory in motion: a study of storage structures in QCA', First Workshop on Non-Silicon Computing, 2002, 2.
    3. 3)
      • M.T. Niemier , P.M. Kogge . Problems in designing with QCAS: layout=timing. Int. J. Circuit Theory Appl. , 1 , 49 - 62
    4. 4)
      • Niemier, M.T., Kogge, P.M.: `Logic in wire: using quantum dots to implement a microprocessor', Int. Conf. on Electronics, Circuits, and Systems (ICECS ’99), September 1999, Cyprus.
    5. 5)
      • Lent, C.S., Tougaw, P.D., Porod, W.: `Quantum cellular automata: the physics of computing with arrays of quantum dot molecules', PhysComp 94: Proc. Workshop on Physics and Computing, 1994, IEEE Computer Society Press.
    6. 6)
      • Blair, E.P., Lent, C.S.: `Quantum-dot cellular automata: an architecture for molecular computing', Int. Conf. on Simulation of Semiconductor Processes and Devices SISPAD 2003, Sept. 2003, 2, p. 14–18.
    7. 7)
    8. 8)
      • Berzon, T.J., Fountain, D.: `A memory design in QCAS using the squares formalism', Proc. Ninth Great Lakes Symp. VLSI ’00, March 1999, p. 166–169.
    9. 9)
    10. 10)
      • Compano, R., Molenkamp, L., Paul, D.J.: ‘Technology roadmap for nanoelectroincs’, in European Commission IST programme, Future and Emerging Technologies.
    11. 11)
    12. 12)
    13. 13)
      • Dimitrov, V.S., Jullien, G.A., Walus, K.: `Quantum-dot cellular automata carry-look-ahead adder and barrel shifter', IEEE Emerging Telecommunications Technologies Conf., 2002.
    14. 14)
      • Tougaw, P.D., Lent, C.S.: `A potentially implementable FPGA for quantum dot cellular automata', Workshop on Non-Silicon Computation (NSC-1), 1994, Boston, MA.
    15. 15)
      • Ottavi, M., Pontarelli, S., Vankamamidi, V., Lombardi, F.: `Design of a QCA memory with parallel read/serial write', Proc. IEEE Computer Society Ann. Symp. on VLSI, May 2005, p. 292–294.
    16. 16)
      • ‘International Technology roadmap’, 2003, http://public.itrs.net/.
    17. 17)
      • Niemier, M.T., Rodrigues, A.F., Kogge, P.M.: `A potentially implementable FPGA for quantum dot cellular automata', Workshop on Non-Silicon Computation (NSC-1), 2002, Boston, MA, USA.
    18. 18)
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